Metal-insulator-metal capacitor

Details Metal-insulator-metal capacitor Metal-insulator-metal capacitor

1999-04-07

2001-05-15

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Planar capacitor

C438S258000

Reexamination Certificate

active

06232197

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an embedded capacitor fabrication and, more particularly, to a method for forming a metal-insulator-metal capacitor in logic circuit.
2. Description of the Prior Art
In the field of integrated circuits, it is preferable to form circuit elements in the smallest achievable surface area in order to realize a high degree of circuit complexity into a small integrated circuit chip size, resulting in low cost per function. The mixed-mode process can provide a process flow with embedded capacitor in logic circuit. The addition of a capacitor can be used for an RC analog circuit or other special applications
Referring to
FIG. 1
, a metal-oxide-semiconductor field effect transistor having a gate
14
C, gate oxide
14
D, drain
14
B and source
14
A is formed in and on a substrate
10
. Further, a bottom electrode
20
of capacitor is formed on a field oxide region
12
. Dielectric layer
21
and top electrode
22
are formed in sequence. Then, after interlevel dielectric layer
30
is formed on the semiconductor device, contact
32
is formed in the interlevel dielectric layer
30
.
For a conventional mixed-mode process, the material of top electrode
22
and bottom electrode
20
is polysilicon. However, the polysilicon depletion will cause the different capacitance values under different bias voltage, as shown in FIG.
2
.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a metal-insulator-metal capacitor that can effectively solve the unstable capacitance problem of poly capacitor.
It is another object of the present invention that the excellent global planarization can also be achieved with this method
In one embodiment, the bottom electrode of the capacitor is formed on a field oxide region first. Then, an interlevel dielectric layer is deposited on the semiconductor device and a portion of the interlevel dielectric layer is then etched Next, having formed a dielectric layer of the capacitor on said bottom electrode, a metal layer is deposited on the dielectric layer Finally, the excess metal layer above the interlevel dielectric layer is removed.


REFERENCES:
patent: 5624864 (1997-04-01), Arita et al.
patent: 6081021 (2000-06-01), Gambino et al.

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