Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2001-01-18
2003-05-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S065000, C257S059000, C257S072000
Reexamination Certificate
active
06566687
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT, and particularly relates to a semiconductor device including a novel top-gate type TFT, a novel top-gate type TFT, and a process for forming a novel top-gate type TFT through metal induced crystallization of amorphous silicon.
2. Prior Art
A thin film transistor (TFT) has been used in wide ranges of semiconductor devices such as an active matrix type liquid crystal display, an organic electroluminescence display, and an image sensors, because a TFT may provide a thin, light weight device with low power consumption. Among TFTs, a TFT, which utilizes polycrystaline silicon (hereafter described as poly-Si), is interested due to its possibility for providing a large area, high resolution device with low production costs.
Conventionally, poly-Si is formed on a substrate such as glass, metal, metal oxide, single crystal silicon by solid phase crystallization or laser crystallization. Typical solid phase crystallization includes steps of depositing an amorphous silicon (a-Si) layer, and heating the layer from about 400 Celsius degrees to 550 Celsius degrees between several hours and several tens hours to crystallize the a-Si layer. In turn, typical laser crystallization includes steps of irradiating the a-Si layer to fuse a-Si at irradiated spots, and re-crystallizing Si upon cooling to ambient temperature.
FIG. 1
shows a process for the solid phase crystallization applied to a top-gate type TFT. In the conventional process, as shown FIG.
1
(
a
), the a-Si layer
102
is deposited on a substrate
101
and then the Ni layer
103
is deposited thereon by a suitable deposition technique. The substrate
101
together with the deposited layers are then subjected to annealing from 400 Celsius degrees to 550 Celsius degrees, thereby crystallizing the a-Si layer to the poly-Si layer
104
induced by a crystal structure of the Ni layer
103
as illustrated in FIG.
1
(
b
). In the described case of FIG.
1
(
b
), crystal boundaries
104
a,
104
b
are formed randomly in the poly-Si layer
104
. Next, the conventional process proceeds to the gettering process shown in FIG.
1
(
c
) and the Ni layer
103
is subjected to HF treatment and anneal treatment to remove the Ni layer
103
by gettering process. Thereafter, as depicted in FIG.
1
(
d
), the gate insulating layer
105
is deposited on the poly-Si layer
104
and the gate electrode
106
are formed on the poly-Si layer
104
. Next, the N+ doping is applied by a suitable technique such as reactive ion doping of
31
P
+
to provide source and drain electrodes.
The conventional TFT having the poly-Si layer formed by the conventional metal induced crystallization shows sufficient performance, however, still has disadvantages such as unevenness in both of on-current and off-current because of randomly created crystal boundaries in the poly-Si layer. In addition, since the removing process of Ni after depositing thereof and the doping process are needed to form the device and then the production process becomes rather complicated.
Japanese patent publication (Laid Open) Heisei No. 7-45519 discloses a semiconductor device and a process for forming thereof, wherein poly-Si is generated by crystallization of a-Si by annealing at the temperature lower than the crystallization temperature of a-Si or lower than a glass transition temperature of a given glass substrate using islands deposited with Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au, Ag, or silicides thereof. These islands act as seeds for crystallization and the resulted crystal boundaries are formed under the controlled manner. The disclosed semiconductor device exhibited a sufficient performance, however, the crystal boundaries still have randomness so that the unevenness in the on- and off-currents may be caused. The production process still requires removing step of the Ni layer and also requires the doping step.
Japanese Patent Publication (Laid Open) Heisei No. 9-213966 discloses a process for forming a semiconductor device, wherein an a-Si layer is crystallized using laser irradiation and a TFT device having an poly-Si layer with large crystal size is disclosed. Although the TFT device obtained has sufficient low leak current when the TFT is off. The crystallization by the laser irradiation may improve unevenness of the crystal boundaries and may provide large crystal size in the poly-Si layer as described above, however, the process requires a laser system so that capital investment for constructing an industrial scale plant becomes huge and therefore, directs to elevation of device costs. In addition, though the laser irradiation provides large crystal size in the poly-Si layer, still larger crystal size is desired to improve device properties.
Therefore, it is needed so far to provide a semi-conductor device which the on- and off-current of TFT is improved and that is produced with more simplified process.
It is also needed so far to provide the top-gate type TFT which has improved on- and off-current properties and that is produced with more simplified process.
It is still needed so far to provide a process for forming the TFT which has improved on- and off-current properties and that is produced with more simplified process.
SUMMARY OF THE MENTION
Therefore, it is an object of the present invention to provide the semiconductor device which the on- and off-current of TFT is improved and that is produced with more simplified process.
It is also another object of the present invention to provide the top-gate type TFT which has improved on- and off-current properties and that is produced with more simplified process.
It is still another object of the present invention to provide a process for forming the TFT which has improved on- and off-current properties and that is produced with more simplified process.
The present invention is partly based on the findings that the metal-dopant compound acts excellent electrodes for the top-gate type TFT when the crystallization of a-Si is carried out on the layer formed with metal-dopant compound.
According to the present invention, a semiconductor device comprising a top-gate type thin film transistor (TFT) is provided. According to the present invention, a semiconductor device comprises a top-gate type thin film transistor (TFT), said top-gate type TFT is formed on a substrate and comprises:
an insulating layer deposited on said substrate;
a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer;
a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode;
an ohmic contact layer being formed between said metal-dopant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound;
a gate insulating layer deposited on said poly-Si layer; and
a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.
According to the present invention, said metal-dopant compound may comprise the elements selected from the group consisting of Ni, Fe, Co, Pt, Mo, Ti, B, and P.
According to the present invention, the metal-dopant compound may be NiP or NiB.
According to the present invention, said metal-dopant compound may be NiP and a concentration of P may range from 0.5 at % to 10 at %.
According to the present invention, said metal-dopant compound may be NiB and a concentration of B may range from 0.25 at % to 2.0 at %.
According to the present invention, a light shielding layer may be formed on said substrate and a plurality of said TFTs may be arrayed to form an active matrix in said semiconductor device such that said semiconductor device is used as an active matrix liquid crystal display.
According to the present invention, a plurality of said TFTs may be arrayed to form an active matrix in said se
Andry Paul S.
Libsch Frank R.
Tsujimura Takatoshi
Flynn Nathan J.
Scully Scott Murphy & Presser
Sefer Ahmed N.
Trepp, Esq. Robert M.
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