Metal I/O ring structure providing on-chip decoupling...

Details Metal I/O ring structure providing on-chip decoupling... Metal I/O ring structure providing on-chip decoupling...

2007-06-05

2007-06-05

Quach, T. N. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular chip input/output means

C257S207000, C257S773000, C257SE23153

Reexamination Certificate

active

11145984

ABSTRACT:
There are provided a metal I/O ring structure for a semiconductor chip and a decoupling capacitance structure using the same. In the Metal I/O ring structure, a plurality of first metal lines are formed on a first metal layer and connected with a power supply voltage, and a plurality of second metal lines are formed on the first metal layer and connected with a ground voltage. The second metal lines are arranged neighboring to the first metal lines. The second metal lines are connected with a second metal layer disposed below the first metal lines on the metal layer, and the first metal lines are connected with the second metal layer disposed below the second metal lines on the first metal layer. An insulating layer is disposed between the first metal layer and the second metal layer, thereby forming a decoupling capacitance between the first metal lines and the second metal lines.

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patent: 5959320 (1999-09-01), Torgerson et al.
patent: 6664634 (2003-12-01), Thompson et al.
patent: 7037820 (2006-05-01), Booth et al.
patent: 2003/0161128 (2003-08-01), Masuda
patent: 1020000003885 (2000-01-01), None
patent: 2003-0069890 (2003-08-01), None

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