Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-10-19
2002-08-27
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S926000
Reexamination Certificate
active
06440868
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing, and more particularly, to the formation of metallic gate electrodes using the replacement gate process technique.
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, metal-oxide-semiconductor (MOS) transistors have typically been formed utilizing polysilicon gate electrodes. Polysilicon material has been preferred for use as an MOS gate electrode due to its thermal resistive properties (i.e., polysilicon can better withstand subsequent high temperature processing). Polysilicon's robustness during high temperature processing allows polysilicon to be annealed at high temperatures along with source and drain regions. Furthermore, polysilicon's ability to block the ion implantation of doped atoms into a channel region is advantageous. Due to the ion implantation blocking potential of polysilicon, polysilicon allows for the easy formation of self-aligned source and drain structures after gate patterning is completed.
However, polysilicon gate electrodes have certain disadvantages. For example, polysilicon gate electrodes are formed from semiconductor materials that suffer from higher resistivities than most metal materials. Therefore, polysilicon gate electrodes may operate at much slower speeds than gates made of metallic materials. To partially compensate for this higher resistance, polysilicon materials often require extensive and expensive silicide processing in order to increase their speed of operation to acceptable levels.
A need exists in the industry for a metal gate device which can replace a polysilicon gate device. However, metal gates can not withstand the higher temperatures and oxidation ambients which can be withstood by conventional polysilicon gate electrodes. In efforts to avoid some of the concerns with polysilicon gate electrodes, a replacement damascene metal gate process has been created. A damascene gate process uses a disposable gate, which is formed with a source, drain, spacer, etch stops and anti-reflective coatings as in conventional processing. However, the disposable gate and dielectrics are etched away, exposing an original gate oxide. The disposable polysilicon gate is then replaced by a metal gate to achieve the lower resistivity provided by the metal material.
A design consideration in semiconductor technology is that of the work function, which is the amount of energy required to excite electrons across a threshold. Polysilicon gates on silicon substrates provide a work function that allows the gates to be adequately controlled. The use of metal, however, as the gate material on a silicon substrate undesirably changes the work function in comparison to polysilicon gates. This reduces the controllability of the gate.
SUMMARY OF THE INVENTION
There is a need for a semiconductor structure and arrangement for making the same in which the gate is made of a metal, but the work function is substantially the same as a semiconductor structure which contains a polysilicon gate.
This and other needs are met by the embodiments of the present invention which provide a semiconductor structure comprising a substrate, active regions in the substrate, and a gate structure on the substrate. This gate structure includes a high dielectric constant (high k) gate dielectric on the substrate, a chemical vapor deposited (CVD) layer of amorphous silicon on the high k gate dielectric, and metal silicide on the CVD amorphous silicon layer.
By providing a semiconductor structure having a gate structure with a CVD layer of amorphous silicon and a metal on the CVD amorphous silicon layer, the advantages of a metal gate, including that of lower resistivity, is achieved without compromising the work function of the gate structure. Hence, the CVD amorphous silicon layer causes the work function of the metal gate to appear like a standard gate.
The earlier stated needs are also met by embodiments of the present invention that provide a method of forming a semiconductor structure, comprising the steps of forming a precursor having a substrate with active regions separated by a channel, and a temporary gate over the channel and between dielectric structures. The temporary gate is removed to form a recess with a bottom and sidewalls between the dielectric structures. Amorphous silicon is deposited in the recess by chemical vapor deposition. The metal is then deposited in the recess on the amorphous silicon. Annealing is then performed to cause the metal and a portion of the amorphous silicon to interact to form metal silicide, with a portion of the amorphous silicon remaining unreacted with the metal.
The formation of a semiconductor structure in accordance with the present invention is advantageous in that high-temperature processes may be performed prior to the deposition of the metal gate. Also, the formation of source and drain electrodes self-aligned to the subsequently formed metal gate is possible. The formation of the metal gate in this replacement gate process, however, allows the metal gate to be formed after the implantation of the dopant atoms. By depositing amorphous silicon in the recess by chemical vapor deposition prior to the depositing of the metal in the recess on the amorphous silicon, the work function will be same as if the gate were made of polysilicon instead of metal. This provides increased control of the gate and avoids leakage.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5960270 (1999-09-01), Misra et al.
patent: 6159782 (2000-12-01), Xiang et al.
patent: 6194748 (2001-02-01), Yu
patent: 6248675 (2001-06-01), Xiang et al.
patent: 410308458 (1998-11-01), None
Besser Paul R.
Buynoski Matthew S.
Xiang Qi
Advanced Micro Devices , Inc.
Trinh (Vikki) Hoa B.
Weiss Howard
LandOfFree
Metal gate with CVD amorphous silicon layer and silicide for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metal gate with CVD amorphous silicon layer and silicide for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal gate with CVD amorphous silicon layer and silicide for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2929166