Metal gate engineering for surface p-channel devices

Details Metal gate engineering for surface p-channel devices Metal gate engineering for surface p-channel devices

2003-09-10

2004-12-14

Nhu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S288000

Reexamination Certificate

active

06831343

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor devices, and in particular, to a method of metal gate work function engineering for surface p-channel devices that eliminates the need for nitrided gate oxides.
2. Description of the Related Art
As is known in the art, MOSFET devices, such as CMOS, have a source and drain region separated by a gate region, all typically formed on a surface of a semiconductive, silicon substrate. Individual devices are typically isolated from each other with isolation structures. Overlying the gate region is a gate stack.
The gate stack enables an overlying conductor to apply a biasing voltage through the gate stack to selectively create and disable a conductive channel between the source and drain regions. Gate stacks typically are multi-layered structures designed to electrically isolate the conductor from the substrate such that minimal current flows through the gate terminal. A dielectric layer, such as silicon oxide, is typically placed above the semiconductor substrate. Then, an interconnecting conductive layer is placed above the dielectric for contact to the conductive layer. The interconnecting conductive layer provides a low resistance, preferably ohmic, contact with the conductor. The composition of the interconnecting layer is typically selected to exhibit good adhesion with both the conductive layer and the underlying dielectric layer and to be compatible with other processing steps and materials. The layers are also chosen to mitigate undesired reactions with adjacent layers in subsequent heat steps that take place during the device fabrication and packaging as well as during use.
The amount of biasing voltage required to enable/disable the conductive channel under the gate is referred to as the threshold voltage (V
t
). An additional design goal for most applications is that the threshold voltages for the NMOS and PMOS devices be complementary. Achieving complementary threshold voltages typically requires that the work function of the gate stack overlying NMOS devices be lower than the underlying p-type doped semiconductor and higher than the underlying n-type doped semiconductor in PMOS devices.
Achieving differential work functions in the gate stacks overlying the NMOS and PMOS regions places the respective Fermi levels closer to mid-gap between the gate stack and the underlying doped substrate. The known alternative to forming differential work functions in the gate stacks is to modify the work functions of the underlying channels regions through doping. Effectively doping the channel regions typically requires relative high doping levels which increases the bulk conductivity and leads to higher undesirable leakage currents.
One known prior art method of forming a gate stack, illustrated in
FIG. 1
for a CMOS device, consists of layering a refractory metal conductor over an interconnecting refractory metal nitride over a dielectric layer on the surface of a semiconductive, silicon substrate. In this example, the materials are W/TiN
x
(x<1)/SiOH/Si or W/WN
x
(x<1)/SiOH/Si. The tungsten (W) metal provides low bulk resistivity while tolerating subsequent high temperature processing steps. The SiOH is a nitrided gate oxide. The gate oxide is nitrided to inhibit the adjacent metal rich TiN
x
or WN
x
from reacting with underlying silicon dioxide without nitride in subsequent heat steps. The heat steps can induce metal atoms to migrate and react with the gate oxide where the metal atoms oxidize thus consuming oxygen atoms from the oxide. This results in the gate oxide SiO
2
being transformed into SiO
x
(x<2) which is a less effective insulator and can result in dielectric breakdown which would result in device failure. Whereas the nitrided gate oxide resists this oxygen consumption and retains good insulating characteristics.
A drawback, however, is that the nitrided gate oxide, SiOH, layer in the gate stack is known to degrade the transconductance (g
m
) characteristics of the devices formed with this method. Transconductance is a measure of the small signal amplification of a MOSFET device. Transconductance is the partial differential of drain current with respect to gate voltage and is dependent on the gate capacitance. The transconductance is a measure of the speed of the device and, as is well understood in the art, faster device speed is a desirable feature. The gate stack is preferably formed with as low a junction capacitance as possible in order to increase switching speed. The partially nitrided silicon oxide has a higher dielectric constant that pure silicon dioxide and thus gives an increased capacitance, which correspondingly lowers the device speed.
This prior art process then involves applying photoresist to selectively mask the PMOS regions. Nitrogen is then implanted into the TiN
x
or WN
x
(x<1) areas of the NMOS regions. The work function of the gate stack over the NMOS regions is reduced with increasing nitrogen content in the titanium or tungsten nitride layers. The TiN
x
has a relatively large work function and TiN is near mid-gap. However, this type of metal nitride based metal gate structure has some disadvantages. In particular, the metal rich TiN
x
(x<1) can react with an adjacent tetraethylorthosilicate (TEOS) spacer during subsequent TEOS deposition.
In a similar manner to that previously described with respect to the nitrided gate oxide, titanium atoms can react with the SiO
2
from the TEOS. This reaction consumes oxygen atoms from the silicon oxide resulting in a silicon rich, nonstoichiometric SiO
x
(x<2). The SiO
x
is a less effective insulator than the silicon oxide and can result in incomplete isolation between individual devices and circuit failure. For this reason, typically only a Nit spacer can be used as a Nit spacer is resistant to reaction with the titanium.
However, a Nit spacer is undesirable from the perspective of the increased dielectric constant of the Nit compared to the silicon dioxide of the TEOS spacer. The approximately doubled dielectric constant of the Nit spacer results in fringing fields that are approximately twice as intense as the fringing fields around a comparable TEOS spacer under a comparable electric field. The higher fringing fields around Nit spacers can cause dielectric breakdown of the gate oxide particularly near the edges of the gate oxide. As is well understood in the art, breaking down the gate oxide damages the device and typically causes failure of the device. Thus, a TEOS spacer is more robust than a comparable Nit spacer.
A further drawback to the previously mentioned gate materials arises from the internal stress of the materials and their adhesive characteristics. In particular, any deposited material will possess some degree of residual stress. The stress may be either tensile or compressive. Tensile stress is relieved by the material contracting while compressive stress is relieved by the material expanding. If the stress in a deposited layer exceeds its adhesion to adjacent layers, the layer may physically peal off the underlying/overlying surfaces. This would have dramatic negative effects on the reliability of metal lines and other device structures. Large stress may also give rise to void formation during subsequent thermal cycling. The stress provides an impetus for grain boundary diffusion. Suitable materials must possess sufficient adhesion to adjacent layers to inhibit separation due to stress.
The TiSi
x
N
y
previously described has good adhesion characteristics, however it has a very high stress level (>15 GD/cm
2
). The WSi
x
N
y
has low stress (<5 GD/cm
2
), however, it suffers from poor adhesive characteristics. As previously mentioned, poor adhesion can also result in a layer becoming dislodged from adjacent layers and resultant device failure.
From the foregoing, it can be appreciated that there is a need for a method of forming a gate stack of materials with good adhesion characteristics and low stress. There is also a need for a method o

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