Metal gate compatible electrical antifuse

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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C257SE23149

Reexamination Certificate

active

08004060

ABSTRACT:
A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

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patent: 2007/0007621 (2007-01-01), Omura et al.
patent: 2008/0116505 (2008-05-01), Wang

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