Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-11-22
2002-07-16
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C439S065000
Reexamination Certificate
active
06420664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sheet of metal foil having bumps, a circuit substrate having the sheet of metal foil, and a semiconductor device having the circuit substrate which are used for manufacturing a semiconductor chip.
2. Description of the Related Art
A chip size package is a semiconductor device, the size of which is substantially the same as that of a semiconductor chip. Therefore, the chip size package is characterized in that the mount area can be remarkably reduced. In this chip size package, it is necessary to provide an arrangement by which thermal stress generated between the mount substrate and the semiconductor chip is reduced. Accordingly, various arrangements to reduce the thermal stress have been proposed.
Electrode terminals of the semiconductor chip are very fine and arranged very densely. On the other hand, external connection terminals such as solder balls are larger than the electrode terminals. Therefore, it is necessary to arrange the external connection terminals in such a manner that the arranging intervals of the external connection terminals are longer than those of the electrode terminals, and the external connection terminals are usually arranged on the overall electrode terminal carrying surface in the formation of an area array.
FIG. 22
is a view showing an example of the arrangement of the electrode terminals
12
of the semiconductor chips
10
and also showing an example of the arrangement of the lands
14
to which the external connection terminals such as solder balls are joined. The lands
14
are arranged in such a manner that the arranging intervals of the lands
14
are longer than those of the electrode terminals
12
, and the electrode terminals
12
and the lands
14
are electrically connected with each other by the wiring sections
16
.
When the land
14
is connected to the external connection terminal, it is common to adopt an arrangement having a cushioning function which is composed in such a manner that, for example, a metal post is vertically attached onto the land
14
and the external connection terminal is joined to an upper end portion of the metal post. Also, the following arrangement is adopted. On an electrode terminal carrying surface of the semiconductor chip, there is provided a buffer layer for reducing thermal stress, and a land of the wiring pattern film, which has been made to adhere via the buffer layer, is joined to the external connection terminal such as a solder ball, so that the cushioning function can be provided.
In the case of a circuit substrate on which a flip chip type of semiconductor chip is mounted, or in the case of a mount substrate on which a surface mount device such as a chip size package is mounted, the connection electrodes such as solder bumps are very densely arranged. Therefore, it is impossible to electrically connect all the connection electrodes to the wiring patterns when the wiring layer is formed into a single layer. For the above reasons, the wiring patterns are formed into a multiple layers in the above cases.
In order to form the circuit substrate into a multiple layers, there is provided a buildup method in which wiring patterns, which are interposed between insulating layers, are electrically connected with each other while the insulating layers are being successively laminated so that a multiple layer can be formed. Also, there is provided a method in which a multilayer of circuit substrates, on which the vias and the wiring pattern are previously formed, are laminated on each other so that a multiple layer can be formed.
In this connection, in order to manufacture a semiconductor device having a fine pattern such as a chip size package, it is necessary to conduct machining with high accuracy.
For example, in the case where wiring is conducted on the electrode terminal carrying surface of the semiconductor chip so as to form the connection electrode having a predetermined pattern and an external connection terminal is joined to the connection electrode, it is necessary to conduct fine machining in which metal posts for supporting the external connection terminals are formed. In the case where an insulating layer having a wiring pattern, which is also used as a buffer layer, is formed on the electrode terminal carrying surface of the semiconductor chip, it is necessary to provide a wire bonding process or a lead bonding process for electrically connecting the electrode terminals of the semiconductor chip with the wiring patterns.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above problems caused when the surface mount devices such as a semiconductor chip and a chip size package are mounted. It is an object of the present invention to provide a sheet of metal foil having bumps, a circuit substrate having the sheet of metal foil, and a semiconductor device having the circuit substrate capable of easily obtaining a mount structure in which the external connection terminals and the connection electrodes can be electrically connected with each other even when the external connection terminals, which are electrically connected to the electrode terminals, are formed on the electrode terminal carrying surface of the semiconductor chip.
In order to accomplish the above object, the present invention is composed as follows.
The present invention provides a sheet of metal foil having bumps characterized in that: bumps, which are electrically connected to connection electrodes provided on one face of a surface mount device such as a semiconductor chip or a chip size package, are arranged in the same plane arrangement as that of said connection electrodes, and protruded onto one side of said sheet of metal foil.
Also, the present invention provides a sheet of metal foil having bumps, wherein lands to which the external connection terminals are joined, which respectively correspond to the bumps, are formed on the other side of said sheet of metal foil.
Also, the present invention provides a sheet of metal foil having bumps, wherein wiring patterns are formed for electrically connecting the bumps to the lands with each other, to which the external connection terminals are joined, and are supported on supporters which couple adjacent wiring patterns.
Also, the present invention provides a sheet of metal foil having bumps, wherein the external connection terminals respectively corresponding to the bumps are formed on the other side of said sheet of metal foil being protruded.
Also, the present invention provides a sheet of metal foil having bumps, wherein wiring patterns are formed for electrically connecting the bumps to the external connection terminals with each other, and are supported on supporters which couple adjacent wiring patterns.
Also, the present invention provides a sheet of metal foil having bumps, wherein the external connection terminals are made of conductive material different from that of said sheet of metal foil.
Also, the present invention provides a sheet of metal foil having bumps, wherein an insulating adhesive agent layer is formed on one side of said sheet of metal foil.
Also, the present invention provides a sheet of metal foil having bumps, wherein tips of the bumps are protruded from a surface of the insulating adhesive agent layer.
Also, the present invention provides a sheet of metal foil having bumps, wherein a carrier tape is made adhere onto the other side of said sheet of metal foil.
Also, the present invention provides a circuit substrate of a multiple layer characterized in that: bumps, which are electrically connected to connection electrodes provided on one face of a surface mount device such as a semiconductor chip or a chip size package, are arranged in the same plane arrangement as that of said connection electrodes and protruded onto one side of the sheet of metal foil; on which wiring patterns, which are electrically connected to the said bumps with each other, are formed; and an insulating adhesive agent layer is made to adhere onto one face of the
Kojima Norio
Muramatsu Shigetsugu
Ogawa Yoshihiko
Cuneo Kamand
Norris Jeremy
Shinko Electric Industries Co. Ltd.
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