Metal film protection of the surface of a structure formed...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material

Reexamination Certificate

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C438S702000, C438S745000, C438S625000, C438S419000, C257S763000, C257S762000

Reexamination Certificate

active

06649498

ABSTRACT:

The present invention concerns the field of microstructures and in particular microstructures made via CMOS technology on semiconductor substrates intended to undergo micro-machining by wet chemical etching.
In the field of certain specific applications, micro-machining is commonly achieved by wet chemical etching of a semiconductor substrate, such as a silicon substrate, on which CMOS elements, such as integrated circuits, have previously been formed. Integrated sensors, in particular, are produced in this manner, such as pressure sensors, including for example a membrane which is formed by making a cavity in the semiconductor substrate. The integrated circuits of the sensor are formed on a first face or front face of the semiconductor substrate, and the second face or back face on which a masking layer resistant to the etchant used has previously been deposited, is subjected to chemical etching by a suitable etchant. A silicon semiconductor substrate can thus be etched by a KOH etchant, the masking layer being for example a film formed of silicon nitride.
In such applications, the face of the semiconductor substrate on which the integrated circuits are formed includes zones capable of being etched by the reactive agent of the etchant. In particular, the substrate may include connection pads formed of aluminium which can be etched by the KOH reactive agent. As a result it is necessary to protect such zones. Mechanical protective equipment is thus typically used such as stainless steel or Teflon™ equipment, arranged on the front face of the substrate including the zones capable of being etched by the KOH reactive agent.
A typical drawback of micro-machining by KOH chemical etching thus lies in the use of such mechanical equipment to protect the zones concerned, and in the fact that such use involves wafer by wafer processing, which is contrary to the usual concerns as to cost and yield in the semiconductor industry.
It will be noted that other etchants are available to those skilled in the art, such as TMAH (Tetra-Methyl-Ammonium Hydroxide) or EDP (Ethylene Diamine Pyrocatechol) to replace the KOH. These etchants do not have the drawback of etching the aluminium connection pads and thus do not require the use of mechanical protective equipment. However, these agents have non-negligible drawbacks.
Indeed, with respect to the KOH etchant, the EDP and TMAH etchants are more expensive and less stable. The stability of KOH is of the order of several months, and those of TMAH and EDP etchants is of the order of several hours and several minutes respectively. It will also be noted that it is suspected that the EDP etchant has carcinogenic properties.
Recently, techniques have been developed to protect the front face of the substrate against etching by the KOH etchant by means of thin protective films deposited on this surface. An article entitled “Fluorocarbon film for protection from alkaline etchant” by Y. Matsumoto, derived from a conference in Chicago entitled TRANSDUCERS 97, describes for example the use of an additional protective layer formed of fluorocarbon.
One drawback of using a component such as fluorocarbon lies in the fact that it require the use of additional equipment to implement it in an industrial environment in which it is not commonly used.
Another drawback of using such a component lies in the fact that it is not compatible with the conventional photolithographical steps, since this component requires the use of a specific resist. Moreover, it has been observed that this resist is capable of becoming easily detached, so that it cannot be used as a photolithographical mask.
Another disadvantage of known protective techniques against etching by the KOH etchant relying on protective films deposited on the surface of the substrate, lies in the fact that they are typically incompatible with the standard process for forming electric connection bumps, in particular electric connection bumps made of gold, this standard process being commonly called “gold bumping”.
One object of the present invention is thus to propose a protection of the surface of a structure formed on a semiconductor substrate, this protection giving the surface of the structure resistance to etching by the KOH etchant and overcoming the aforementioned drawbacks.
Another object of the present invention is to propose a protection of this type which is also compatible with the standard methods of forming electric connection bumps, and in particular gold bumping.
Another object of the present invention is to propose a protection of this type which also answers the conventional criteria in the semiconductor industry linked to cost, yield and to the environment, as regards the materials used to form this layer.
The present invention therefore concerns a structure formed on a semiconductor substrate intended to be etched by a KOH etchant whose characteristics are listed in claim 1.
The present invention also concerns a method of manufacturing such a structure the characteristics of which are listed in claim 7.
The present invention also concerns a method of manufacturing an integrated sensor with a dielectric membrane the characteristics of which are listed in claim 8.
Advantageous embodiments of the present invention form the subject of dependent claims.
One advantage of the present invention lies in the fact that the protective film covers the different zones capable of being etched by the KOH etchant, in particular the aluminium connection pads, which gives the structure protection against this etchant. This results in a high manufacturing yield.
Another advantage of the present invention lies in the fact that the protective film gives resistance to the reactive etchant, so that the structure can undergo processing by batches of wafers, i.e. without using additional mechanical equipment to protect this structure wafer by wafer.
A further advantage of the present invention lies in the fact that the protective film is perfectly compatible with gold bumping.


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