Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-06-13
2004-02-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S773000, C257S767000, C257S768000, C257S770000, C257S751000, C257S752000, C438S702000, C438S703000
Reexamination Certificate
active
06690093
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a metal contact structure in a semiconductor device and a method for forming the same.
2. Description of the Related Art
A conventional semiconductor device is formed by stacking a predetermined number of conductive layers and an interlayer dielectric film on a semiconductor substrate. The conductive layers include wiring which is typically constructed using polycrystalline silicon doped with impurities. Alternatively, metals such as W, Al, Cu, or metal silicide, which have excellent conductive characteristics, can be used as the wiring material. In general, a metal wiring structure includes wiring longitudinally extended in a horizontal direction parallel to the surface of a substrate and two or more contact structures for connecting regions of a substrate, such as termination points, or for connecting vertically arranged conductive layers together in a vertical direction. The contact structure consists of an upper conductive layer (upper wiring) and a lower conductive layer (lower wiring), between which is interposed an interlayer dielectric film. Included in this contact structure is a hole having a conductive plug, which extends from the upper to the lower conductive layers. This conductive plug can be deposited into the previously etched hole during the deposition of the upper wiring. When the contact plug is formed using a metal material, it is referred to as a “metal contact plug.”
As the integration density of a semiconductor device increases, the width of a conductive layer (the wiring) is reduced accordingly, and the precision and uniformity of the line width must be more rigidly controlled in the formation of the metal contact structure.
FIG. 1
illustrates a sectional end view of a metal contact structure of a conventional dynamic random access memory (DRAM). A metal conductor
28
is formed of W as the upper conductive layer, and is connected to a drain region
12
on a substrate
10
through a conductive pad
18
of a lower conductive layer
20
. Although conductor
28
may be directly connected to the drain region
12
without pad
18
for lower density structures, this becomes impractical for higher integration densities. As the distance between a pair of gate electrodes
14
becomes smaller, the use of a pad
18
, which is formed by a self alignment method using sidewall spacers
16
of the gate electrodes
14
is widely used.
In the contact structure, conductor
28
fills a contact hole
22
′ and is in contact with the pad
18
. Barrier metal
24
and
26
are thinly formed on the bottom and sidewalls of the contact hole
22
′ between the conductor
28
and the pad
18
. The barrier metal layers
24
and
26
may be referred to as an ohmic layer
24
and a barrier layer
26
.
A method for forming a metal contact structure is as follows. After forming the pad
18
and an interlayer dielectric film
22
, which covers the pad
18
, a contact hole
22
′, which exposes some of the pad
18
, is formed by etching the interlayer dielectric film
22
. The ohmic layer
24
formed of Ti and the barrier layer
26
formed of TiN are formed over the entire surface of the interlayer dielectric film
22
including contact hole
22
′. A W layer is formed over the entire surface of barrier layer
26
, and the conductor
28
is completed by patterning the form of conductor
28
and etching to remove all non-patterned regions of the W layer, the ohmic layer
24
, and the barrier layer
26
, excluding the region under conductor
28
.
As the integration density increases, the width of the conductor
28
, that is, the W layer left after performing etching, is reduced. Furthermore, as shown in
FIG. 1
, the conductor
28
may not completely cover the contact hole
22
′ thereby exposing some of the sidewalls of the contact hole
22
′. When conductor
28
does not completely cover contact hole
22
′, etching gas mainly formed of SF
6
that is used during the etching of conductor
28
reacts with the Ti of ohmic layer
24
, at the bottom of contact hole
22
′. Accordingly, a TiFx portion
24
′, which is an insulating material, is formed, thereby increasing contact resistance.
Additional disadvantages of using conventional fabrication techniques in higher density integration applications include misalignment of etching masks and increased inter-electrode capacitances that occur as conductor separation distances are reduced.
SUMMARY OF THE INVENTION
It is a feature of an embodiment of the present invention to provide a metal contact structure of a semiconductor device, which protects contact holes from incomplete coverage by overlaying conductive layers, including a preferred method for construction thereof.
It is another feature of an embodiment of the present invention to provide a method for forming a metal contact structure of a semiconductor device that has the above structure.
Accordingly, a metal contact structure of a semiconductor device includes a lower conductive layer, an interlayer dielectric film, which is formed on the lower conductive layer and in which a contact hole exposing some of the lower conductive layer is formed, a metal upper conductive layer connected to the lower conductive layer through the contact hole, insulating layer spacers on the sidewalls of the upper conductive layer, and barrier metal layers interposed between the upper conductive layer and the lower conductive layer. The barrier metal layers, aligned with the first spacers, are formed on the bottom and the sidewalls of the contact hole under the upper conductive layer and on the surface of the interlayer dielectric film under the first spacers, and extend beyond the width of the upper conductive layer.
In another embodiment of the present invention, an upper conductive layer formed of a metal is formed by etching a metal layer, which is formed on the entire surface of an interlayer dielectric film and fills a contact hole, and etching is stopped when a barrier layer under the metal layers is exposed. Preferably, the barrier layer is a barrier metal layer. After forming spacers on the sidewalls of the upper conductive layer, the barrier metal layers are removed by using the spacers as etching masks. More specifically, the contact hole that exposes some of a lower conductive layer is formed by forming the lower conductive layer and the interlayer dielectric film that covers the lower conductive layer and etching the interlayer dielectric film. The barrier metal layers are formed on the entire surface of the interlayer dielectric film including the contact hole. The metal layer is formed on the entire surface of the barrier metal layers. The upper conductive layer is formed by etching the metal layer to have a predetermined pattern until the barrier metal layers are exposed. The spacers formed of an insulating material are formed on the sidewall of the upper conductive layer. The barrier metal layers are etched until the interlayer dielectric film is exposed using the spacers as the etching masks and thus, are removed.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
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Ahn Tae-hyuk
Kim Myeong-cheol
Erdem Fazli
Flynn Nathan J.
Lee & Sterba, P.C.
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