Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2001-02-09
2004-06-29
Ngo, Julie (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S039000, C349S148000
Reexamination Certificate
active
06757031
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a thin film transistor liquid crystal display (TFT-LCD) and method of forming the same, and more particularly, to a metal contact structure and method for thin film transistor array in liquid crystal display in order to prevent source/drain electrode metal layer from plasma damage and oxide insulator formation thereon during contact hole etching process, such that low contact resistance is obtained between the source/drain electrode metal layer and top ITO conductive layer.
BACKGROUND OF THE INVENTION
An active matrix LCD device is typically composed of a matrix of liquid crystal pixels with a thin film transistor array that serves as the switching element of the pixels to effect optical characteristics of the pixel liquid crystal for image display by the control of the thin film transistor. The applications for LCD are very appreciated due to their thin in volume and low power consumption. However, local defects in the thin film transistor array for large-scale sized LCD devices could easily result in a reduced yield due to the large-scale area. The manufacture of the thin film transistor array therefore has high impact on the yield of the LCD devices.
On the other hand, the prior art replaces conventional processes with the one that uses one less mask to increase throughput for the TFT-LCD manufacture. In addition, an ITO (In
2
SnO
5
) conductive layer is often employed to cover on top surface of the whole thin film transistor structure to electrically connect the pixel electrode with the source/drain electrode thereof, in order to decrease the manufacturing steps for thin film transistor array, reduce the possibility of short circuit between elements, and increase the open ratio of the display device. In a five-mask process prior art for the thin film transistor array, the etching depths of the first and second metal layers in the contact hole etching process are different, the second metal layer will thus suffer from serious plasma damage by the contact hole etching process. Moreover, an oxide insulator layer could be formed on the second metal layer during the contact hole etching process, resulting in a further degradation of contact resistivity.
A structure of the conventional 5-mask thin film transistor is shown in
FIG. 1
for illustration, whose manufacturing process comprises forming a gate electrode
11
on a transparent substrate
10
and then depositing a gate insulator layer
12
that is further deposited with an intrinsic semiconductor layers
13
and a doped semiconductor layer
14
thereon. A source/drain electrode metal layer
15
is deposited, patterned, and etched after the semiconductor layers
13
and
14
are patterned and etched. Then, the doped semiconductor layer
14
is etched, and an insulative passivation layer
16
is deposited over the structure. Contact holes
18
and
19
are formed in the passivation layer
16
by etching process. An ITO conductive layer is finally deposited, patterned, and etched.
The etching depths of the top and bottom metal layers
15
and
11
during the contact hole etching process are different, as shown in the figure, the formation of the contact hole
18
needs to etch through the passivation layer
16
and insulator layer
12
, while only the passivation layer
16
is etched for the contact hole
19
. When the contact hole
18
is satisfied, the top metal layer
15
suffers from plasma damage, thereby increasing the contact resistivity between the metal layer
15
and the top ITO layer
17
in the contact hole
19
. Moreover, over-etching is often employed in the prior art to obtain a sufficient etching depth of the contact hole
18
, so that the metal layer
15
is more seriously damaged. Further, an oxide insulator layer could be formed on top surface of the metal layer
15
in the contact hole
19
during the plasma etching of the contact hole
19
, which will increase the contact resistivity between the metal layer
15
and the top ITO conductive layer
17
due to the insertion of the residue oxide insulator layer into the contact structure.
To resolve such problems, there have been disclosed several methods, such as chemical wet etching process, instead of plasma dry etching process, is employed to form the contact holes. However, the controllability of wet etching is worse than that of dry etching, and the contact hole formed by wet etching is larger than that by dry etching. Another prior art comprises an additional physical dry processing or chemical wet processing to remove the plasma-damaged layer and oxide insulator layer on the top surface of the second metal electrode, while such process will bring in more systematic complexity and another damages to the device.
Pan et al. improved the method of forming TFT-LCD with multi-layer metal electrode in Taiwan Pat. Application No. 88107676, which increases the etching selectivity of the insulative passivation layer to the contact layer of the multi-layer metal, in order to depress the etching damage to the multi-layer metal in the formation of the contact holes. However, Pan et al. did not know the damage to the source/drain electrode metal due to the different etching depths of the different metal layers in this prior art. Pan et al. also did not disclose the recipe for the high etching selectivity process, which seems to be a chemical wet etching. In addition, the oxide insulator layer formed during the etching process to form the contact holes has never been mentioned in this prior art.
In Japan Pat. Publication No. 11-283934, Kazunori et al. provided a method comprising surface treatment to the exposed contact region of the electrode metal layer after etching the contact holes, in order to remove the residue material comprising oxygen or carbon formed on the contact surface, thereby decreasing the contact resistivity. Similarly, Kazunori et al. did not know the damage to the source/drain electrode metal due to the different etching depths of the different metal layers, thus they cannot prevent the electrode metal layer from plasma damage during the contact hole etching process, except for removing the insulator layer formed on the electrode metal.
These prior arts can not simultaneously resolve the problems of plasma damage to the source/drain electrode metal due to the different etching depths of the different contact holes and the oxide insulator formation during the contact hole process. Therefore, it is desired a metal contact structure and method for thin film transistor array in liquid crystal display in order to prevent the source/drain electrode metal layer from plasma damage and oxide insulator formation thereon during the contact hole etching process, such that low contact resistance is obtained between the source/drain electrode metal layer and top ITO conductive layer.
SUMMARY OF THE INVENTION
An object of the present invention is to disclose a metal contact structure and method for thin film transistor array in liquid crystal display, by which the source/drain electrode metal layer thereof is prevented from plasma damage and oxide insulator formation thereon during the contact hole etching process, such that low contact resistance is obtained between the source/drain electrode metal layer and top ITO conductive layer.
According to the present invention, a thin film transistor comprises a gate electrode formed on a transparent substrate with a gate insulator layer covered on the gate electrode and an intrinsic semiconductor layer and a doped semiconductor layer formed on the gate insulator layer, and a source/drain electrode metal layer formed on the doped semiconductor layer with a metal oxide conductive film covered thereon. An insulative passivation layer covers on the transistor structure with a contact hole formed thereof through the passivation layer to reach the metal oxide conductive film, and a transparent top ITO conductive layer is formed on the passivation layer and electrically connects with the metal oxide conductive film in the contact hole.
For forming the thin f
Lan Wei-Chou
Lin Wen-Jian
Ngo Julie
Prime View International Co. Ltd.
Thomas Kayden Horstemeyer & Risley
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