Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1999-07-29
2004-03-09
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S618000, C438S690000, C438S700000, C257S780000, C257S781000, C257S786000
Reexamination Certificate
active
06703286
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a novel method of creating a metal bond pad for low-k Inter-Metal Dielectric.
(2) Description of the Prior Art
The continuation of increased demands for semiconductor circuit performance brings with it a continuation of increased demands for smaller device features and increased circuit packaging densities.
High density interconnect technology addresses the field of increased circuit packaging density where many integrated circuit chips are physically and electrically connected to a single substrate commonly referred to as a multi-chip module (MCM). To achieve a high wiring and packing density, it is necessary to fabricate a multilayer structure on the substrate to connect integrated circuits to one another. Typically, layers of a dielectric such as a polyimide separate metal power and ground planes in the substrate. Embedded in other dielectric layers are metal conductor lines with vias (holes) providing electrical connections between signal lines or to the metal power and ground planes. Adjacent layers are ordinarily formed so that the primary signal propagation directions are orthogonal to each other.
For many of the advanced semiconductor devices, device signals such as ground, power and I/O signals require numerous bonding pads. With the increased density of components within a chip and with increased sophistication of the circuitry contained within the chip, further demands are placed on the number of bonding pads for each chip. For many designs, the number of bonding pads becomes the limiting factor on chip size and chip function.
Improvements in packing density cannot be realized by simply shrinking the design rules or adding more levels of metal wiring.
Aluminum grows a passivating oxide layer in air and is as a consequence protected against corrosion. Aluminum wiring used in semiconductors, however, contains copper, which does not have a passivating oxide, and the Al—Cu alloy used is more vulnerable to corrosion. The corrosion of aluminum wires is caused by several sources such as chlorine transported through the plastic packaging and the passivation materials, chlorine from the etching compounds and as etching by-products, phosphorous acid formed from excess phosphorous in the phosphosilicate glass, etc. Only a small amount of chlorine is required to cause severe local corrosion of the aluminum lines. Aluminum corrosion can, in addition, occur very quickly after metal etching.
To avoid etching introduced corrosion, chlorine compounds and elemental chlorine must be removed from the metal surface immediately after plasma etching. A water rinse or a water vapor treatment usually accomplishes this.
Modern metal structures use multi-levels of dissimilar materials such as Ti/TiN/Al—Cu/TiN or Ti/Al—Cu/TiN, which increases the possibility of electromechanical corrosion.
Copper is electro-positive with respect to hydrogen and is not vulnerable to corrosion. However, in air copper oxide grows linearly with time, indicating the lack of a protective oxide. This lack of a passivating oxide makes copper more vulnerable to chemical corrosion. To avoid or minimize this corrosion, most applications of copper metalization involve some protective layer deposited on top of the copper.
In the production of high-density semiconductor devices, a primary concern of manufacturing is the creation of simple, reliable, and inexpensive bond pads is. Bond pads are disposed on a planar surface and provide a location for bonding wires or other connectors that are wired to device elements located in the semiconductor die substrate. The semiconductor die is in this manner wired to components external to the die. In one typical case, a bonding wire is attached to the bonding pad at one end and a portion of the lead frame at the other. Any improvement which simplifies the manufacturing process, enhances the reliability, or reduces the costs of bond pads can provide a competitive advantage to those involved in the commercial manufacture of semiconductor devices.
A typical application of a bond pad is where aluminum is exposed and used for the bond pad. A (gold) bonding wire can be bonded to this aluminum pad. Where ambient temperatures are relatively low, for instance less than approximately 150 degrees C., the physical attachment and the electrical connection between the gold wire and the aluminum pad remain sufficiently reliable. Where ambient temperatures increase above 150 degrees C., the bonding between the aluminum pad and the gold bonding wire rapidly degenerates. This is caused by the formation of gold and aluminum intermetallics that are caused by diffusion between the two metals resulting in the formation of aluminum-gold chemical compositions. Porosity, delamination, and voiding can now take place at the bonding interface. This effect is further emphasized by further increases in temperature over time resulting in the eventual failure of the interconnecting bond.
A basic requirement for bond pads is that they provide a maximum number of I/O interconnect locations. Intersection of wires that are used to make these I/O connections is thereby not desired (since these wires would now have to be electrically isolated further adding to the processing cost) which leads to an arrangement for the bond pads around the periphery of the final package. Materials used for the bond pads include metallic materials such as tungsten and aluminum while heavily doped polysilicon can also be used for contacting material. The bond pad is formed on the top surface of the semiconductor device whereby the electrically conducting material is frequently embedded in an insulating layer of dielectric. In using polysilicon as the bond pad material, polysilicon can be doped with an n-type dopant for contacting N-regions while it can be doped with p-type dopant for contacting P-regions. This approach of doping avoids interdiffusion of the dopants and dopant migration. It is clear that low contact resistance for the bond pad area is required while concerns of avoidance of moisture or chemical solvent absorption, thin film adhesion characteristics, delamination and cracking play an important part in the creation of bond pads. For these reasons extra steps, such as the creation of a metal seed layer and diffusion barrier layers (of Ti or TiN) within the openings created for the deposition of the bond pad, are often taken if metal (tungsten, aluminum) is used for the bond pad. These additional processing steps have various objectives such as improvement of adhesion of the deposited bond pad material, to serve as wetting layers to improve the flow of the metal into the bond pad cavity, the improvement of contact resistance and to form a diffusion barrier to avoid the migration of silicon (from the substrate) into the bond pad area.
The present invention relates generally to bond pads that are fabricated on a semiconductor die. More specifically, during formation of a bond pad, the shape of the bonding pad is altered where one (large) pad is divided into many (smaller) pads, the (smaller) pads that belong to the same interconnect level are interconnected. The new method avoids the presence of large amounts of the low-k IMD dielectric on the top surface of the pad since most of the IMD flows into the cavities between the (smaller) pad surfaces. Vias are created over the (smaller) pads thus enabling the typical bond pad interconnect function.
FIG. 1
a
shows a top view of a Prior Art bond pad arrangement
10
where in number of bond contact vias
12
have been created.
FIG. 1
b
shows a cross section of the metal bond pad
10
over which a layer
14
of HSQ IMD has been deposited, the cross section is taken along the line
2
-
2
′ of
FIG. 1
a
. HSQ/MSQ are typical low-k IMD's that are used for this application. These dielectric materials are prone to moisture absorption and the absorption of chemical solvents during device processing such as the creation of via patte
Liu Chung-Shi
Yu Chen-Hua
Ackerman Stephen B.
Deo Duy-Vu
Kunemund Robert
Saile George O.
Taiwan Semiconductor Manufacturing Company
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