Meta-stable free flipflop

Details Meta-stable free flipflop Meta-stable free flipflop

1990-06-11

1991-03-19

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 307452, H03K 3356, H03K 3037

Patent

active

050013718

ABSTRACT:
A flipflop circuit is responsive to a clock signal for latching the terminal logic state of the input signal at an output irrespective of the relative transistions of the input data signal and the clock signal thereby providing immunity from the meta-stable condition. The input data signal is propagated from the input through a first stage to an intermediate node during a first clock cycle. A boost signal is applied at the intermediate node via first or second transistors for driving the potential developed thereat toward the terminal logic state of the input data signal. The logic state stored at the intermediate node may be used as the output signal or passed through additional buffer stages to an output during subsequent cycles of the clock signal.

REFERENCES:
patent: 4591737 (1986-05-01), Campbell
patent: 4629909 (1986-12-01), Cameron

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