Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-06-14
2011-06-14
Alrobaye, Idriss N (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S011000, C712S010000
Reexamination Certificate
active
07962717
ABSTRACT:
Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.
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International Search Report and Written Opinion, dated Jun. 19, 2008.
Alrobaye Idriss N
Sughrue & Mion, PLLC
XMOS Limited
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