Message passing distributed shared memory system that eliminates

Details Message passing distributed shared memory system that eliminates Message passing distributed shared memory system that eliminates

1997-01-24

2000-09-12

Maung, Zarni

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

711141, G06F 15167, G06F 1300

Patent

active

061191507

ABSTRACT:
An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

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