Multiplex communications – Wide area network – Packet switching
Patent
1993-09-30
1995-07-11
Chin, Wellington
Multiplex communications
Wide area network
Packet switching
379134, 379133, 370 60, H04M 1508, H04M 1510, H04M 1504
Patent
active
054327768
ABSTRACT:
A digital message routing network has at least some nodes at which messages are monitored for accounting purposes. Such a node contains means for generating and compressing accounting digests, each of which consists of a key K representing the nature and route of the message and a value V associated with the message. For each message, a digest is produced in register 30, and copied into a location in a first memory 22D at a location determined by hashing its key; further digests with the same key are compressed into the digest already in that location. A second memory 23D is operated as a cyclic buffer with head and tail counters HDCT 40 and TLCT 41. The address of the head of the buffer, ie the valid area of memory 23D, is included as an index I in each digest in the first memory 22D as that digest is created. Each time a digest is created or changed in the first memory 22D, it is copied into the second memory at the location in the second memory determined by its index. Digests are read out from the second memory in blocks; the corresponding digests in the first memory thereby become invalid, and have to be restarted by initializing their values and giving them new indexes.
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Chin Wellington
Digital Equipment Corporation
Kozik Kenneth F.
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