Message header classifier

Multiplex communications – Wide area network – Packet switching

Patent

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Details

370 941, H04Q 1104, H04J 324

Patent

active

053943945

ABSTRACT:
The classifier device disclosed herein analyzes message headers of the type which comprise a sequence of bit groups presented successively. The device employs a read/write memory for storing at a multiplicity of addresses, an alterable parse graph of instructions. The parse graph instructions include node instructions which comprise opcodes in association with respective next address characterizing data and terminator instructions which comprise identifying data for previously characterized header types. A logical processor responds to a node instruction read from memory either by initiating another memory read at a next address which, given the current state of the processor, is determinable from the current node instruction and the current header bit group or by outputting data indicating recognition failure if no next address is determinable. The logical processor responds to a terminator instruction by outputting respective header identifying data. Accordingly, for a previously characterized header type, a corresponding pattern of node instruction and a terminator instruction can be written into memory thereby enabling the device to identify the respective header type in a time which is essentially proportional to the length of the header and thus also to the time of presentation of the header. The parse graph can be updated dynamically during the operation of the classifier.

REFERENCES:
patent: 4933937 (1990-06-01), Konishi
patent: 5136580 (1992-08-01), Videlock et al.
patent: 5229994 (1993-07-01), Balzano et al.
patent: 5237564 (1993-08-01), Lespagnol et al.
patent: 5249178 (1993-09-01), Karano et al.

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