Electrical computers and digital processing systems: multicomput – Multicomputer data transferring via shared memory
Reexamination Certificate
2004-07-07
2009-10-06
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: multicomput
Multicomputer data transferring via shared memory
C712S011000
Reexamination Certificate
active
07599998
ABSTRACT:
A data processing apparatus comprises at least one source processor core, at least two destination processor cores, a message handler and a bus arrangement providing a data communication path between the source core, the destination cores and the message handler. The message handler has plurality of message-handling modules. At least one of the message-handling modules has a message receipt indicator that is modifiable by each of the destination processor cores to indicate that a message has been received at its destination. This message-handling module also has a transmission completion detector operable to detect, in dependence upon a message receipt indicator value that a message has been received by all of the at least two destination processor cores and to initiate transmission of an acknowledgement signal to the source processor core.
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Fearnhamm Harry Samuel Thomas
Galbraith Mark James
Mathewson Bruce James
Smith Nicholas Esca
ARM Limited
Chan Eddie P
Nixon & Vanderhye P.C.
Petranek Jacob
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