Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
1997-12-16
2001-07-03
Geckil, Mehmet B. (Department: 2152)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C710S262000
Reexamination Certificate
active
06256677
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer systems and in particular to a network-based computer system.
BACKGROUND
Modular, highly interconnected computer network systems offer the ability to exchange data among individual nodes in the network and to share hardware resources. Many networks move large amounts of data and many messages between the nodes on the network. Due to the large amounts of data movement in such a system, communication traffic among the nodes can become congested. Messages and data are sent in self-contained packets which have the needed address, command and data. Packets can be sent from a source to a target through several intermediate nodes. This saves time and congestion since the processors do not wait for each message to travel the length of the network before sending the next packet.
There are still problems associated with messages sent from a source to a target in a network computer system. One of the problems is that latency or time delays can be caused in central processing units which are either the source or target for multiple messages. Currently, as each message packet is received, it produces an interrupt. The central processing unit must respond to each interrupt before the next message can be received. This is not a problem in many computer systems. However, in network-based systems, multiple messages may have to be received by a central processing unit at any given time. Multiple messages produce multiple interrupts. In the instance when multiple messages arrive at a central processing unit at about the same time, the CPU is only capable of handling the messages serially and must respond to an interrupt for a first message and service the interrupt before the next message interrupt can be responded to and serviced. When multiple messages arrive at a CPU, the CPU may spend an inordinate amount of time processing the various interrupts associated with the messages. This problem is exacerbated in a network-based system where it is more common for a particular CPU to have to process multiple messages. When a CPU or central processing unit has to service a number of messages, many times latency can be introduced into the particular computer system. In other words, the CPU which has to service multiple messages is spending more time servicing interrupts associated with the multiple messages than doing other operations. The other operations can be delayed as a result, and this is referred to as latency due to system overhead and results in an increased response time of a particular central processing unit. There is a need for a central processing unit for use in a network system that can efficiently receive and handle multiple messages. There is also a need for a CPU that can handle multiple messages in a stream and which can handle multiple messages with one pass through its operating system. There is also a need for a system or CPU which can handle multiple messages with one interrupt. Such a system could check to see if additional messages have arrived while a first interrupt for a message is being processed. There is also a need for a CPU that spends less time servicing multiple interrupts from multiple messages and spends more of its time on other jobs. There is also a need for a computer system that has a reduced set of instructions for dealing with the receipt of packets or messages from a network. There is also a need for a more efficient way to send messages to a target client computer on a network and to receive messages or packets from the network. Such a system would handle messages more effectively which would produce a network having increased speed and lower overhead in terms of an instruction set and clock cycles being used.
SUMMARY OF THE INVENTION
A computer for use in a network system has a communication controller for controlling the receipt and sending of packets or messages at each client computer. The interface associated with each client computer includes a send message buffer and a receive message buffer. The send message buffer has a send message buffer counter which increments upwardly in response to messages being received from the client computer for sending on the ring network. The communication controller sends messages from the send buffer until the send message buffer counter reaches the address or a value associated with the last received message. Similarly, the receive message buffer includes a receive message buffer counter which increments as each message is received to a receive message buffer counter value. The receive message buffer is emptied until the receive message buffer counter value is reached. The receive buffer can also have an active portion and an inactive portion. This can also be called a foreground portion and a background portion. The communication controller continually switches between the active and inactive portions of memory and redesignates each memory portion after the switch. The communications controller can also recognize priority schemes for the messages.
Advantageously, the communication controller allows for minimal interference when transferring messages. The communication controller allows for minimal interruption of this processor when transferring messages in and out of a receive buffer or send buffer. Since the communication controller increments a receive packet counter (RPC) within the receive buffer when messages are input to a buffer to produce a counter having an address or a value associated therewith that is reflective of the last received message, when outputs need to be sent from the send buffer, the communication controller can merely send messages until the value of the counter is equal to the value associated with the limit address for a particular message. When the counter value equals the address associated with the limit of the message, then the communication controller stops sending messages. The advantage is that in the past, various flags and interrupts had to be used to indicate when a single message was complete. For example, if four messages had to be sent, four interrupts would be processed by the processor from the communications controller to receive the four messages. Under the current communications controller, time is saved since the messages into the buffer do not require the processing of an interrupt. The messages are received and an RPC counter is incremented to reflect the receipt of the message. Therefore, several messages can be processed after an initial interrupt has begun processing. The subsequent messages do not need to process an interrupt. If subsequent messages are received in memory, the RPC may be incremented before the CPU completes the previous interrupt. By the same token, when sending messages out of the send buffer, a number of message end interrupts do not have to be processed. The end result is that multiple messages or packets can be sent or received into the receive buffers, with minimal overhead and minimal processing.
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Bravatto James G.
Bye Michael T.
Kline John Theodore
Pribnow Richard D.
Geckil Mehmet B.
Schwegman Lundberg Woessner & Kluth P.A.
Silicon Graphics Inc.
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