Message-based low latency circuit emulation signal transfer

Details Message-based low latency circuit emulation signal transfer Message-based low latency circuit emulation signal transfer

2011-04-12

2011-04-12

Trost, IV, William (Department: 2472)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C326S047000, C703S028000, C710S006000, C716S136000

Reexamination Certificate

active

07924845

ABSTRACT:
Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.

REFERENCES:
patent: 5036473 (1991-07-01), Butts et al.
patent: 5109353 (1992-04-01), Sample et al.
patent: 5406554 (1995-04-01), Parry
patent: 5541918 (1996-07-01), Ganmukhi et al.
patent: 5563829 (1996-10-01), Huang
patent: 5604739 (1997-02-01), Buhrgard et al.
patent: 5625625 (1997-04-01), Oskouy et al.
patent: 5777489 (1998-07-01), Barbier et al.
patent: 5821773 (1998-10-01), Norman et al.
patent: 5896380 (1999-04-01), Brown et al.
patent: 5923656 (1999-07-01), Duan et al.
patent: 6044211 (2000-03-01), Jain
patent: 6064677 (2000-05-01), Kappler et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6198723 (2001-03-01), Parruck et al.
patent: 6265894 (2001-07-01), Reblewski et al.
patent: 8265894 (2001-07-01), Reblewski et al.
patent: 6473726 (2002-10-01), Reblewski
patent: 6731638 (2004-05-01), Ofek
patent: 2001/0052793 (2001-12-01), Nakaya
patent: 2002/0031086 (2002-03-01), Welin
patent: 2003/0053435 (2003-03-01), Sindhushayana et al.
patent: 2003/0099242 (2003-05-01), Shah et al.
patent: 2003/0125907 (2003-07-01), Saint-Hilaire et al.
patent: 2003/0144828 (2003-07-01), Lin
patent: 2004/0030816 (2004-02-01), Knight et al.
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 0 651 343 (1995-05-01), None
patent: WO 94/06210 (1994-03-01), None
Charles Clos, “A Study of Non-Blocking Switching Networks”, The Bell System Technical Journal, Mar. 1953, pp. 406-424.
Werner Erhard et al., “First Steps towards a Reconfigurable Asynchronous System”, Friedrich-Schiller University Jena, Department of Computer Science, IEEE International Workshop on Rapid System Prototyping, Jun. 1999, pp. 28-31.
Fatih Kocan et al., “Concurrent D-Algorithm on Reconfigurable Hardware”, IEEE 1999, pp. 152-155.
Jack Jean et al., “Dynamic Reconfiguration to Support Concurrent Applications”, IEEE Transactions of Computers, vol. 48, No. 8, Jun. 1999, pp. 591-802.
Bernard Bosi et al., “Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 3, Sep. 1999, pp. 299-308.
A. Ejnioui et al., “Design Partitioning on Single-Chip Emulation Systems”, Center for Microelectronics Research, Dept of CSE, University of South Florida, 13thInternational Conference on VLSI Design, 2000, pp. 234-239.
Greg Snider, “The Teramac Compiler”, Hewlett-Packard, 1996, pp. 1-51.
Xilinix, “Programmable Gate Array Design Handbook”, First Edition, 1986, pp. I-A10.
Jonathan Babb, et al., “Logic Emulation with Virtual Wires”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jun. 1997, pp. 1-20.

Affiliated with

Also associated with

Rating

Message-based low latency circuit emulation signal transfer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Message-based low latency circuit emulation signal transfer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Message-based low latency circuit emulation signal transfer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2683774