Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Patent
1997-01-09
1998-09-22
Sparks, Donald
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
174255, 174257, 361792, H05K 103, H05K 109, H05K 116
Patent
active
058123806
DESCRIPTION:
BRIEF SUMMARY
The invention relates to a multilayer module including an on-module capacitor for producing stabilized power performance and noise reduction for the electronic components therein.
Multilayer modules are used for the packaging of electronic components, especially integrated circuit chips. Both single chip modules (SCM) and multi chip modules (MCM) are widely used. The most common type of such modules is the multilayer ceramic packaging module. In this type of module the layers of the module consist of a ceramic or glass-ceramic material. However, other types of thickfilm technology are known, such as glass epoxy and teflon.
The basic technology of multilayer modules was first described by A. J. Blodgett and D. R. Barbour "Thermal Conduction Module: A High-Performance Multilayer Ceramic Package," IBM Journal of Research and Development 26 (1), pp. 30-36 January 1982 and by A. J. Blodgett, "Microelectronic Packaging," Scientific American, 249 (1), pp. 86-96, January 1983. These articles are incorporated herein by reference. The technology of multilayer modules is also described in "microelectronics packaging handbook", edited by R. R. Tummala and E. J. Rymaszewski, New York, 1988, especially in chapter 7 entitled "Ceramic Packaging", pp. 455-522 which is also included herein by reference.
As integrated circuit speeds and packaging densities increase, the importance of the packaging technology becomes increasingly significant. For example, as devices approach gigahertz speed, inductance effects and the like in the packaging become more significant. Such inductance effects may arise from, for example, switching and the like, and are particularly problematic in power and ground leads. Inductance effects in the package can cause ground bounce, signal cross-talk and the like. Increasing circuit size and speed also impact the heat dissipation ability of the packaging.
VLSI and ULSI chips are designed for high performance applications and are thus particularly limited by noise. The noise is caused by a high number of simultaneous switching off-chip drivers (OCD noise) and by a high number of simultaneous switching latches and the associated logic gates (logic noise). Both noise sources impact and restrict the on-chip and off-chip performance and jeopardize the signal integrity. Both noise sources generate noise due to line to line coupling and due to the collapse of the voltage-ground (GND) system. It is known in the art, to use on-module capacitors to stabilize the power system. Thereby a major noise reduction is achieved.
FIG. 1 shows a cross section through a standard multilayer ceramic module. The module 13 comprises the layers L11, L12, L13, . . . , L17, . . .
A first ground plane GND is interposed between the layers L12 and L13. A first voltage plane VH is interposed between the layers L13 and L14. Between the layers L14 and L15 there is a first redistribution plane R1 and between the layers L15 and L16 there is a second ground plane GND. Between the layers L16 and L17 there is a second redistribution plane R2. A typical multilayer multichip module has about 5 redistribution planes which are followed by the signal distribution layers, also called "X/Y wiring area". In contrast a single chip module generally only has redistribution planes for the fanout of the wiring and not signal distribution layers.
Between the topmost layer L11 and the second topmost layer L12 there is no significant wiring due to restrictions of the technology. In particular, it is not possible to interpose a ground or voltage plane between the layers L11 and L12 according to the prior art. Hence, on the backside of the layer L11--which is denoted LB1--there is no or only very little wiring such as for test purposes.
The integrated circuit chip 10 shown in FIG. 1 has a plurality of C4--balls 11 which serve to connect the integrated circuit chip 10 to the module 13. The decoupling capacitor Cm 12 has also C4 balls 11 which serve to connect the decoupling capacitor 12 to the module 13. In the example shown in FIG. 1 the integrated circuit ch
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Frech Roland
Garben Bernd
Harrer Hubert
Klink Erich
Ehrlich Marc A.
International Business Machines - Corporation
Sparks Donald
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