Mesh interconnected array in a fault-tolerant computer system

Details Mesh interconnected array in a fault-tolerant computer system Mesh interconnected array in a fault-tolerant computer system

1996-06-06

1998-04-21

Beausoliel, Jr., Robert W.

3951851, 39518401, 39518222, 39518509, G06F 1100

Patent

active

057427534

ABSTRACT:
Bus interface units (BIUs)(54) perform fault detection, identification, and reconfiguration for all information transfers between redundant central processing units (CPUs)(56) and memory or input/output (I/O)(57A-C) in a mesh interconnected array of a highly reliable fault-tolerant computer system. Errors are detected by self-checking within the BIUs, signal parity checks by the BIUs, cross channel comparisons, and mesh transaction assessments. Fault identification and mesh reconfiguration for the mesh is performed such that no faulty unit remains active in decision making after reconfiguration, and the number of good units isolated during reconfiguration is minimized.

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