1988-06-02
1990-01-16
Mintel, William
357 41, 357 22, H01L 2702
Patent
active
048946923
ABSTRACT:
An integrated circuit includes a semi-insulating semiconductor substrate; a first conductivity type high dopant concentration buried layer produced in the semi-insulating substrate; second conductivity type high dopant concentration drain and source regions produced at the surface of the semi-insulating substrate; a gate electrode produced on the surface of the semi-insulating substrate at a position between the drain and source regions; a second conductivity type channel layer produced between the drain and source regions; and a first conductivity type low dopant concentration region produced only below the second conductivity type channel layer between the second conductivity type drain and source regions in the first conductivity type high dopant concentration region; the drain and source regions being completely surrounded by the first conductivity type high dopant concentration buried layer from the bottom and outer side surfaces thereof. Alternatively, a first conductivity type high dopant concentration buried layer is provided only below and at outer side surfaces of the drain layer and a first conductivity type low dopant concentration buried layer is provided below the channel layer and the source region and at the outer side surface of the source region.
REFERENCES:
patent: 3886583 (1975-05-01), Wang
patent: 4377756 (1983-03-01), Yoshihara et al.
Noda Minoru
Tanino Noriyuki
Mintel William
Mitsubishi Denki & Kabushiki Kaisha
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