Patent
1978-04-21
1980-05-06
Wojciechowicz, Edward J.
357 22, 357 41, 357 49, 357 50, H01L 2948
Patent
active
042019974
ABSTRACT:
An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath a thick field oxide, depletion and enhancement mode device channel implants, implanted source and drain regions, selective oxidation to form self-aligned gates, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.
REFERENCES:
patent: 4104672 (1978-08-01), DiLorenzo et al.
patent: 4139786 (1979-02-01), Raymond et al.
Darley Henry M.
Houston Theodore W.
Kruger James B.
Donaldson Richard L.
Hiller William E.
Texas Instruments Incorporated
Williamson Ronald A.
Wojciechowicz Edward J.
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