Mesfet latch circuit

Details Mesfet latch circuit Mesfet latch circuit

1987-10-28

1989-11-28

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 3072721, 307291, H03K 326, H03K 19017

Patent

active

048839850

ABSTRACT:
An FET circuit suitable for a latch has a pair of inverters. The input stage FET of each of the inverters is connected such that the gate electrode thereof is connected to receive an output signal of the FET of the other inverter through a circuit having an FET and at least a diode. The sources of the input stage FETs are connected to a common connection point, and a current source arrangement such as a resistor is connected between the common connection point and a power supply terminal. The circuit provides an extended allowable range of the effective threshold voltage V.sub.T and has small power consumption.

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Katsu et al., "GaAs Monolithic Frequency Divider Using Source Coupled FET Logic", IEE Elec. Devices Letters, vol. EDL-3, No. 8, Aug. 82, pp. 197-199.
Chu et al., "Low-Power, High-Speed Sense Latch", IBM Tech. Discl. vol. 17, No. 9, Feb. 75, pp. 2582-2583.
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