Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1999-09-07
2001-05-22
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S194000, C257S195000, C257S287000, C438S172000
Reexamination Certificate
active
06236070
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to Gallium Arsenide (GaAs) field effect transistors (FETs) and more particularly, to a FET employing both metal-semiconductor (MES) and metal-insulator-semiconductor (MIS) gates for improved voltage breakdown and output power capabilities.
BACKGROUND OF THE INVENTION
GaAs MESFETS are well known devices for providing amplification at microwave frequencies, high speed digital switching, and various other functions. The use of microwave frequencies in satellite and wireless communications has been growing exponentially over recent years, thereby providing a vast market for GaAs transistors. As the power output capability of MESFETs continues to improve, a single transistor can provide the power once provided by several, thereby saving considerable costs and drastically reducing the size of the amplifier modules. GaAs transistors are increasingly being used in high power transmitters to replace old designs which employed traveling wave tubes or klystrons. The higher the power handling capability and efficiency that can be achieved, the greater the number of potential applications for MESFET amplifiers. Accordingly, there has been a tremendous effort in the commercial and military industry over recent years to improve the performance capability of these GaAs devices.
The conventional MESFET employs a metal gate electrode in direct contact with a GaAs substrate to form what is known as a Schottky barrier. A voltage applied to the gate electrode influences a current carrying region beneath the gate, thereby controlling the flow of current between the drain and source electrodes and thus providing amplification or switching.
Illustrated in
FIG. 1
is a cross-sectional view of a conventional n-channel MESFET
10
. An n+ source region
14
, n+ drain region
12
, and an n doped channel region
15
are formed within a GaAs substrate
11
. Gate, source and drain electrodes s, g and d, respectfully, are then formed atop the respective doped regions, with the gate electrode g typically offset towards the source electrode s for reduced parasitic source resistance. When a voltage is applied between the gate and source electrodes g and s, it controls a surface depletion region
16
formed within the channel
15
, through which current flows from drain to source upon the application of a bias voltage between the drain and source electrodes.
A basic circuit arrangement for which the MESFET
10
provides amplification of an RF input signal is shown in FIG.
2
. The circuit
20
amplifies the RF input signal applied to input terminal
18
to provide an amplified RF output across a load resistor R
L
. Inductors L
1
and L
2
act as AC chokes to bring the DC bias voltages Vgg and Vdd to the respective gate and drain terminals of the device
10
. Capacitors C
1
and C
2
function as DC blocks, while input and output matching structures
17
and
19
are employed to transform the relatively high input and output system impedances to generally lower device impedances, to optimize the performance of the MESFET
10
.
The load line characteristics of the circuit
20
superimposed on the MESFET
10
I-V characteristics is shown in FIG.
3
. As the RF input signal swings up and down during one RF cycle, so does the gate to source voltage v
GS
which causes the drain to source current i
DS
to increase and decrease, respectively. This results in the drain to source voltage V
DS
being large when the current is small, and vice versa. The load line
21
indicates that the V
DS
swing is from a “knee” voltage Vk to (2VDD−Vk), as i
DS
swings from a maximum current i
P
to a minimum current imin. Basically, the slope and excursion of the load line is governed by the choice of the DC bias voltages VDD and VGG, the value of the load resistance R
L
in conjunction with the output matching network
19
, and the magnitude of the input voltage swing (i.e., the RF input power level). In any event, these parameters must be selected to prevent the voltage v
DS
from swinging too high and penetrating the breakdown region
19
.
To maximize output power, it is desirable to have both a large current swing and a large voltage swing. The maximum current is limited by the channel doping and thickness, while the maximum voltage swing is set by the gate-drain breakdown voltage. One way to increase the gate drain breakdown voltage is to increase the spacing D
1
between the gate electrode g and the drain n+ region
12
(FIG.
1
). This approach was the subject of an article entitled “A Novel High-Voltage High Speed MESFET Using a Standard GaAs Digital IC Process”, by P. Mok et al., IEEE Transactions on Electron Devices, Vol. 41, No. 2, February, 1994. In that article, breakdown voltages above 80V were reported; however, the higher the breakdown voltage which was achieved, the higher the “on-resistance” of the device, a parameter which reduces device efficiency.
A major shortcoming of either of the above approaches to increasing output power—i.e., increasing breakdown voltage or increasing maximum channel current—is that they compete directly with one another. That is, for a given geometry, increasing the channel thickness and/or doping level of the channel to increase the maximum channel current will decrease the gate to drain breakdown voltage. Moreover, increasing the spacing between the gate electrode and the drain n+ region
12
to increase the breakdown voltage actually decreases the maximum channel current. (This latter effect has been measured using a technique of applying short duration voltage pulses between the gate and source in the absence of RF input power, and then measuring the peak i
DS
current. This technique is believed to be more representative of the FET's behavior under RF drive than the conventional method of applying DC voltages to the device to measure the maximum current).
Accordingly, there is a need for a GaAs transistor which has both higher gate-drain breakdown voltage and higher current handling capability to yield higher RF power output performance. It is an object of the present invention to provide such a transistor.
SUMMARY OF THE INVENTION
The present invention is directed towards an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS gate with appropriate biasing allows the carrier density within a selected portion of the device's channel region to be controlled. The carrier density control increases the breakdown voltage of the FET and enables the FET to be operated with higher maximum channel current and a higher drain to source voltage. As a result, higher output power is provided as compared to prior art MESFET devices of a similar size.
The invention is also directed towards an amplifier circuit including the MES/MIS FET of the present invention, which amplifier circuit further includes means coupled to the MES/MIS FET for dividing a high frequency input signal to provide a first divided portion and a second divided portion. The first divided portion is applied to the MES gate while the second divided portion is applied to the MIS gate. The second portion Sacs as a time vying bias voltage to control carrier density within the channel portion of the MES/MIS FET and thereby control performance parameters such as breakdown voltage and maximum available channel current.
REFERENCES:
patent: 4179668 (1979-12-01), Schuermann
patent: 5012315 (1991-04-01), Shur
patent: 5554865 (1996-09-01), Larson
patent: 5633610 (1997-05-01), Maekawa et al.
patent: 6005267 (1999-12-01), Griffin et al.
patent: 53-72475 (1978-06-01), None
Ng, Kwok K., Complete Guide to Semiconductor Devices, McGraw-Hill (Pub), pp. 188-189, Jan. 1995.
Barsan, Radu M., “Analysis and Modeling of Dual-Gate MOSFET's” IEEE Trans. Elec. Dev., vol. ED-28, No. 5, pp. 523-534, May, 1981.
Bahl Inder J.
Griffin Edward L.
Miller Dain Curtis
McDermott & Will & Emery
Mintel William
Tyco Electronics Logistics AG
LandOfFree
MES/MIS FET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MES/MIS FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MES/MIS FET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2468344