Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor
Reexamination Certificate
2011-07-19
2011-07-19
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Layout editor
C716S121000, C716S128000, C326S041000
Reexamination Certificate
active
07984415
ABSTRACT:
Approaches for merging replicate logic blocks of a circuit design. Groups of replicate logic blocks in a placed circuit design are determined. For the replicate logic blocks in each group, a determination is made whether or not to merge replicate logic blocks in a subset of the replicate logic blocks into a respective single replacement logic block for the subset. In response to determining to merge the replicate logic blocks in the subset, the replicate logic blocks in the subset are replaced in the circuit design with the respective replacement logic block. The circuit design having the replacement logic block is stored in a memory by a processor executing the process.
REFERENCES:
patent: 2009/0128189 (2009-05-01), Madurawe et al.
U.S. Appl. No. 11/805,954, filed May 25, 2007, Manaker et al.
U.S. Appl. No. 11/827,531, filed Jul. 12, 2007, Srinivasan et al.
Cartier Lois D.
Levin Naum
Maunu LeRoy D.
Xilinx , Inc.
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