Merged VLSI implementation of hardware optimized Q-Coder and sof

Details Merged VLSI implementation of hardware optimized Q-Coder and sof Merged VLSI implementation of hardware optimized Q-Coder and sof

1997-01-14

1999-01-12

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

To or from code based on probability

341 50, 341 51, 341 61, 341 67, 341106, H03M 700

Patent

active

058596046

ABSTRACT:
The present invention includes a method and circuit for the compression encoding and decoding of digital images. In particular, the method is directed to an improved implementation of the QM-Coder as defined in the JBIG Standard and a merged implementation of the QM-Coder as defined in the JBIG Standard with the Q-Coder as defined by the IBM ABIC standard. The improved implementation of the QM-Coder as defined in the JBIG Standard includes an improved CLEARBITS procedure. The merged implementation of the QM-Coder as defined in the JBIG Standard and Q-Coder as defined by the ABIC standard includes the sharing of hardware to reduce implementation logic.

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