Merged-transistor switch with extra P-type region

Details Merged-transistor switch with extra P-type region Merged-transistor switch with extra P-type region

1982-09-27

1984-12-18

James, Andrew J.

357 35, 357 41, 357 43, 357 44, 357 46, H01L 2702

Patent

active

044893418

ABSTRACT:
In one N-type epitaxial pocket of an integrated circuit there is formed a vertical NPN transistor and two other P-type regions each positioned adjacent but spaced from the P-type base region of the NPN. A metal gate over the gap between the base and one of the other P-type regions forms a high input-impedance P-MOS stage driving the NPN. A metal layer contacts both the NPN emitter and the PNP emitter formed by the third P-type region. This PNP transistor clamps the NPN collector-emitter to a safe voltage when switching an inductive load, and in a particularly efficient manner. A second P-MOS transistor is formed by extending the metal layer over the gap between the NPN-base and the third P-type region which transistor is capable of preventing leakage current out of the input P-MOS transistor in the off state form turning on the NPN transistor.

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Carballo, R. A. and Ing. P. W., "Self-Contained Bipolar-FET Device", IBM Technical Disclosure Bulletin, vol. 19, No. 11, Apr. 1977, pp. 4191-4192.

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