Merged single polysilicon bipolar NPN transistor

Details Merged single polysilicon bipolar NPN transistor Merged single polysilicon bipolar NPN transistor

1997-02-20

1999-07-20

Fahmy, Wael M.

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With specified electrode means

257588, 257592, H01L 27082, H01L 27102, H01L 2970

Patent

active

059259230

ABSTRACT:
A merged single polysilicon bipolar NPN transistor, rather than using separate isolation islands for emitter-base and collector contacts, utilizes a single isolation island. This significantly reduces device area because elimination of the second isolation island used in conventional designs reduces the N+ sink to NPN spacing. Buried layer and isolation layer processing proceed in the conventional manner. At sink mask, however, the mask is sized to uncover one end of the main device active region and a sink implant is performed. At base mask, the sink implant remains covered, rather than being exposed as in the conventional flow. At silicide exclusion, the oxide spacer layer is patterned to exclude silicide from the area above the sink implant region.

REFERENCES:
patent: 5187554 (1993-02-01), Miwa
patent: 5424572 (1995-06-01), Solheim

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