Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1997-12-08
2001-08-07
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S903000
Reexamination Certificate
active
06271542
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to design and fabrication of merged logic circuits and memory arrays on a single semiconductor integrated circuit (IC) chip and, more particularly, to “system on chip” circuits and fabrication methods thereof in which logic circuits use two semi-conductor levels, a thin film level and a bulk silicon (Si) level, and the memory array consists of static random access memory (SRAM).
2. Background Description
Increasing the density of logic circuits and memory arrays leads to faster circuit performance, smaller integrated circuits (ICs), and hence lower cost per IC. Presently, logic and memory functions are made on separate ICs and overall system speed is limited by communication bandwidth between logic and memory. The performance limit of about 500 MHz is due to communication bandwidth, and is a direct result of logic and memory functions communicating over relatively long distances (millimeters).
Also presently, the density of static random access memory (SRAM) arrays at integration levels of 16 megabit (Mb) and 64 Mb and higher is increased by locating four n-type metal oxide semiconductor (NMOS) transistors in the Si wafer level, and two p-type metal oxide semiconductor (PMOS) load transistors in a Thin Film (TF) polycrystalline Si (p-Si) layer above the Si wafer level. See, for example, A. K. Sharma,
Semiconductor Memories
, IEEE Press, New York (1997), and Y. Takao, H. Shimada, N. Suzuki, Y. Matsukawa, and N. Sasaki ,
IEEE Transactions on Electron Devices
39 (1992) p. 2147. The SRAM cell then requires a smaller Si wafer area. This is an example of three-dimensional (3D) integration to achieve higher density, and hence larger integrated SRAM arrays. In the 3D SRAM example, other benefits include increased noise immunity and low standby current, as particularly described by Sharma, supra.
On approach to reach beyond the performance limit of 500 MHz is integration of logic circuits and memory arrays on a single IC. These ICs are known as a “merged logic and memory”, or a “system on chip” configuration. The system on chip configuration can enhance performance. Presently, two distinct process technologies are used to fabricate the distinct logic and memory chips.
What is needed is a solution to both density scaling and enhanced performance and also a single process technology to fabricate the logic and memory circuits.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a compact and economical method to design and manufacture “system on chip” ICs.
It is another object of the invention to provide a single process technology and 3D integration method for both logic and memory circuits.
According to the invention, there is provided merged logic and memory ICs in which the logic circuits are fabricated in two semi-conductor levels, a thin film (TF) level and a bulk Si level. The logic circuits are a three-dimensional form of differential cascode voltage switch (DCVS) logic, in which the PMOS transistors are made in a thin film Si level located above the NMOS transistors, the latter being made in a bulk Si wafer level. This type of logic is described, for example, by L. G. Heller, W. R. Griffin, J. W. Davis, and n. G. Thoma,
Digest Tech. Papers, ISSCC
1984, pp. 16-17, and by Fang-shi Lai and Wei Hwang,
IEEE Journal of Solid
-
State Circuits ,
32 (1997) p. 563. The memory array of this invention consists of static random access memory (SRAM), in which SRAM cell consists of two PMOS load transistors made in the aforementioned thin film Si level located above four NMOS driver transistors, which are located in the aforementioned bulk Si wafer level.
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patent: 5321280 (1994-06-01), Sakai
patent: 5326989 (1994-07-01), Muragishi
patent: 47-16084 (1972-08-01), None
patent: 4-152566 (1992-05-01), None
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patent: 9-45922 (1997-02-01), None
Lai et al., “Design and Implementaion of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems”, IEEE Journal of Solid-State Circuits, vol. 32, No. 4, Apr. 1997, pp. 563-573.
Lai et al., “Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems”, VLSITSA, 1993, pp. 358-362.
Emma Philip George
Gates Stephen McConnell
Hwang Wei
International Business Machines - Corporation
Loke Steven
McGuireWoods LLP
Tassinari, Jr. Robert P.
Vu Hung Kim
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