Merged FinFET P-channel/N-channel pair

Details Merged FinFET P-channel/N-channel pair Merged FinFET P-channel/N-channel pair

2005-07-05

2005-07-05

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

C257S302000, C257S315000, C257S316000, C257S347000, C257S350000, C257S351000

Reexamination Certificate

active

06914277

ABSTRACT:
A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.

REFERENCES:
patent: 6657252 (2003-12-01), Fried et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
U.S. Appl. No. 10/728,844; filed Dec. 8, 2003; entitled: “Merged FinFET Inverter/Logic Gate”; 51 pages.

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