Merged field effect transistor circuit and fabrication process

Details Merged field effect transistor circuit and fabrication process Merged field effect transistor circuit and fabrication process

1979-06-28

1981-10-20

Wojciechowicz, Edward J.

Metal treatment

Stock

Ferrous

357 4, 357 22, 357 23, 357 45, 357 46, 357 47, 357 55, 357 56, 148 15, H01L 2702

Patent

active

042964288

ABSTRACT:
A three dimensional merged field effect transistor device, and circuits incorporating such devices, which are fabricated from two or more bodies of semiconductor material disposed on a carrier or substrate. The structure includes at least two bodies of semiconductor material, each body consisting of material of both a first and a second conductivity type. Each body has two spaced apart surfaces such that a portion of the first surface of the first body is disposed adjacent to a surface of the second body and separated therefrom by a dielectric layer so that the surface portion on the first body forms the gate electrode of a first field effect transistor, and the source, channel, and the drain regions of the first field effect transistor being formed by surface zones on the surface of the second body. On the second surface of the first body there are also three adjacent surface zones of alternating conductivity type which form the source, channel, and drain region of a second field effect transistor. In the first body one of the surface regions forming the source of the second field effect transistor is electrically connected with the surface portion on the second surface forming the gate of the first field effect transistor. More particularly, the first surface zone on the first surface and the first surface zone on the second surface of the first body form a common or merged region or semiconductor material of the same dopant concentration.

REFERENCES:
patent: 4072974 (1978-02-01), Ipri
patent: 4084108 (1978-04-01), Fujimoto
patent: 4107725 (1978-08-01), Yoshida et al.

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