Merged bipolar and insulated gate transistors

Details Merged bipolar and insulated gate transistors Merged bipolar and insulated gate transistors

1989-06-16

1991-07-02

Hille, Rolf

357 42, 357 35, 357 234, H01L 2702, H01L 2972, H01L 2910

Patent

active

050289772

ABSTRACT:
A vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistor is formed in and along one of the sidewalls of the structure. Source and drain regions are formed in the structure by ion-implantation using a polysilicon gate electrode formed over a gate insulator on the sidewall as a self-aligning mask.

REFERENCES:
patent: 4344081 (1982-08-01), Pao et al.
patent: 4717686 (1988-01-01), Vaterstetten et al.
patent: 4737472 (1988-04-01), Schaber et al.
patent: 4739386 (1988-04-01), Tanizawa
patent: 4851889 (1989-07-01), Matsuzaki
patent: 4868135 (1989-09-01), Ogura et al.
"High Speed BICMOS VLSI Technology with Buried Twin Well Structure", IEDM Tech. Digest, 1985, Washington, D.C., pp. 423-426.
"A 2 .mu.m BICMOS Process with Fully Optimized MOS and Bipolar Transistors", ECS 171st Society Meeting, vol. 87-1) May, 1987, Philadelphia, Pa., pp. 407-408.

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