Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-10-12
2003-09-16
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S532000, C257S777000
Reexamination Certificate
active
06621137
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit chip (IC) packaging. More particularly, the present invention relates to the packaging devices with an integrated circuit chip package. In particular, the present invention relates to integrated packaging of a microelectronic device with devices such as switches, capacitors, filters, resonators, inductors, and power supplies.
2. Description of Related Art
One of the difficulties of integrated circuit packaging is that selected large, usually passive devices that may be placed on silicon with an IC, have structures that are not compatible with the integrated fabrication scheme of the traditional active components such as field effect devices and metallization wiring layouts. Among these usually passive devices are included, not by way of limitation, switches, capacitors, resonators, inductors, and power supplies. For example, on an active surface of a device that requires quality factor inductors, it becomes difficult integrate into the fabrication scheme a large-enough conductive structure to have the high inductance (Q) that may be required. Similarly, where a large surface area is needed for a specific capacitor, the real estate cost to place it on the semiconductor device silicon is uneconomical.
Another problem relates to prior art on-chip variable capacitors. These capacitors are based on varactor diode technology that have a tuning range of less than about 25%. The varactor diode technology also has a low pull-in effect. Additionally, prior art membrane capacitors have a capacitance tunable range that is limited due to the voltage exceeding the critical voltage (Vc) thereof. At Vc, the membrane collapses and the capacitor shorts out. Additionally, due to the suspension nature of the prior art capacitors, the center portion of the flexible membrane draws closer to the fixed electrode than the edge portions. This phenomenon creates a greater local capacitance at the center of the flexible membrane than at the edge portions of the flexible membrane where it is anchored. Between capacitors, it is difficult to control capacitance change in any predictable way such as a linear or even a nonlinear functional correlation between the amount of applied direct current (DC). voltage and the resulting capacitance. Where the edge portions of the flexible membrane occupies a substantial capacitance surface area in relation to the center portion, it becomes difficult to achieve an appreciable range of tunable capacitance.
Another need that has arisen is for smaller- and higher-frequency resonators for both signal filtering and signal generating purposes. The prior state of the art used discrete crystals or devices that generate a surface acoustical wave (SAW) for their desired functions. As miniaturization of devices progresses, the discrete crystals and SAW generating devices do not shrink at the same rate. Therefore discrete passive devices ultimately limit how small an RF system can be.
REFERENCES:
patent: 5309014 (1994-05-01), Wilson
patent: 6342724 (2002-01-01), Wark et al.
Cheng Peng
Ma Qing
Rao Valluri
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Potter Roy
LandOfFree
MEMS device integrated chip package, and method of making same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MEMS device integrated chip package, and method of making same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MEMS device integrated chip package, and method of making same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3095221