Memory writer with deflective memory-cell handling capability

Details Memory writer with deflective memory-cell handling capability Memory writer with deflective memory-cell handling capability

1998-03-12

2001-01-23

Hafiz, Tariq R. (Department: 2784)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S152000, C717S152000, C717S152000, C717S152000, C714S006130

Reexamination Certificate

active

06178549

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a method and system for modifying a microprogram-code before writing it into a partially defective memory.
BACKGROUND OF THE INVENTION
In the past, memory chips with defective cells will not be sold in the marketplace. However, with the advent of a number of state-of-art techniques, defective memory chip can behave as a defective-free memory chip. And there are a number of patents addressing methods of using partially defective memories as transparently “good” memories. It is also well known that defective memory-cells can be located by any appropriate testing procedure, such as alternatively writing “1” and “0” in each bit location and then verifying the results.
U.S. Pat. No. 4,939,694 to Eaton et. al., describes a self-testing and self-repairing memory system. The memory system tests itself during field use to locate defective memory-cells. Once these defective memory-cells are located, the memory system uses the error correction code engine to correct these defective memory-cells. When the error correction code engine becomes overburdened, then the memory system replaces these defective memory-cells.
U.S. Pat. No. 5,644,541, to Siu et. al., describes a memory system comprising a plurality of semiconductor memories with some bad bits, a substitution memory and a mapping logic to redirect accesses to bad-bit locations in the semiconductor memories to good storage cells within the substitution memory.
U.S. Pat. No. 5,278,847, to Helbig, Sr. and Anastasia, describes a fault-tolerating memory system that uses an error-detecting-and-correcting (EDAC) code. The reliability of storage is greatly improved by extension of each word to add EDAC encoding and spare-bit portions, as well as by extension of depth to allow spare words to be present, along with high-reliability storage of word maps.
U.S. Pat. No. 5,579,266 to Tahara, handles defective memory by use of laser repair, or programmable fuse repair, and replaces defective memory-cells with redundant rows and columns.
Executable machine code are typically generated from the source code of a computer program by the compile and link operations. As the executable machine code is obtained, it is ready to be loaded into memories for program execution.
It is observed that, the error checking and error correcting techniques, or memory re-direct techniques, provided by some of the prior arts inevitably adds overhead to the hardware design and/or program execution each time the executable machine code is executed. On the other hand, the redundant memories, circuits and the defective memory repair work provided by some prior arts also add design and operation complications.


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