Memory with word-line driver circuit having leakage...

Details Memory with word-line driver circuit having leakage... Memory with word-line driver circuit having leakage...

2007-10-31

2009-08-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185230, C365S227000, C365S228000

Reexamination Certificate

active

07577054

ABSTRACT:
In a semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection thereof, a word driver circuit that drives the word line has a drive PMOS transistor and drive NMOS transistor which are connected in series between a first node and a second node and each of which has a gate connected to a third node, the word line being connected to a connection node of the two transistors. A first voltage or a second voltage lower than the first voltage is then applied to the third node, and the first voltage or second voltage is applied to the first node. In addition, between the third node and the gate of the drive PMOS transistor, there is provided a leakage prevention NMOS transistor having a gate applied with the first voltage or a voltage in the vicinity thereof.

REFERENCES:
patent: 6809986 (2004-10-01), Kim et al.
patent: 2003/0039143 (2003-02-01), Ogane
patent: 2006/0198231 (2006-09-01), Larguier et al.
patent: 2006/0239108 (2006-10-01), Shimizu et al.
patent: 2008/0123463 (2008-05-01), Matsubara
patent: 10-312682 (1998-11-01), None
patent: 11-86543 (1999-03-01), None

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