Memory with trench capacitor and selection transistor and...

Details Memory with trench capacitor and selection transistor and... Memory with trench capacitor and selection transistor and...

2002-02-28

2003-12-16

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S243000, C438S387000, C438S294000, C438S299000, C438S300000, C257S346000, C257S396000

Reexamination Certificate

active

06664167

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a trench capacitor with a selection transistor and a corresponding fabrication method. The invention is explained with regard to a trench capacitor that is used in a DRAM memory cell. For discussion purposes, the invention is described in respect of the formation of an individual memory cell.
Integrated circuits (ICs) or chips contain capacitors for the purpose of storing charge, such as, for example, a dynamic random access memory (DRAM). In such a case, the charge state in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells that are disposed in the form of rows and columns and are addressed by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is realized by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor includes, inter alia, two diffusion regions isolated from one another by a channel that is controlled by a gate. Depending on the direction of current flow, one diffusion region is referred to as the drain and the other as the source. The source region is connected to a bit line, the drain region is connected to the trench capacitor and the gate is connected to a word line. By the application of suitable voltages to the gate, the transistor is controlled such that a current flow between the drain region and the source region through the channel is switched on and off.
The charge stored in the capacitor decreases over time on account of leakage currents. Before the charge has decreased to a level below a threshold value, the storage capacitor must be refreshed. For this reason, these memories are referred to as dynamic RAM (DRAM).
The central problem in prior art DRAM variants based on a trench capacitor is the production of a sufficiently large capacitance for the trench capacitor. The problem will be aggravated in future by the advancing miniaturization of semiconductor components. The increase in the integration density means that the area available per memory cell and, thus, the capacitance of the trench capacitor decrease ever further.
Sense amplifiers require a sufficient signal level for reliably reading out the information situated in the memory cell. The ratio of the storage capacitance to the bit line capacitance is crucial in determining the signal level. If the storage capacitance is too low, the ratio may be too small for generating an adequate signal.
A lower storage capacitance likewise requires a higher refresh frequency, because the quantity of charge stored in the trench capacitor is limited by its capacitance and additionally decreases due to leakage currents. If the quantity of charge falls below a minimum quantity of charge in the storage capacitor, then it is no longer possible for the information stored therein to be read out by the connected sense amplifiers, the information is lost, and read errors arise.
One way of avoiding read errors is to reduce the leakage currents. Leakage currents can be reduced on the one hand by transistors and on the other hand by dielectrics, such as the capacitor dielectric, for example. An undesirably reduced retention time can be lengthened by these measures.
Stacked capacitors or trench capacitors are usually used in DRAMs. Examples of DRAM memory cells having a trench capacitor are given in U.S. Pat. No. 4,649,625 to Lu, U.S. Pat. No. 5,065,273 to Rajeevakumar, U.S. Pat. No. 5,512,767 to Noble, Jr., U.S. Pat. No. 5,641,694 to Kenney, U.S. Pat. No. 5,658,816 to Rajeevakumar, U.S. Pat. No. 5,691,549 to Lam et al., U.S. Pat. No. 5,736,760 to Hieda et al., U.S. Pat. No. 5,744,386 to Kenney, and U.S. Pat. No. 5,869,868 to Rajeevakumar.
A trench capacitor has a three-dimensional structure that is formed in a silicon substrate, for example. An increase in the capacitor electrode area and, thus, in the capacitance of the trench capacitor can be achieved, for example, by etching more deeply into the substrate and, thus, by deeper trenches. In such a case, the increase in the capacitance of the trench capacitor does not cause the substrate surface occupied by the memory cell to be enlarged. However, this method is also limited because the attainable etching depth of the trench capacitor depends on the trench diameter, and, during fabrication, it is only possible to attain specific, finite aspect ratios between the trench depth and trench diameter.
As the increase in the integration density advances, the substrate surface available per memory cell decreases ever further. The associated reduction in the trench diameter leads to a reduction in the capacitance of the trench capacitor. If the capacitance of the trench capacitor is dimensioned to be so low that the charge that can be stored is insufficient for entirely satisfactory readout by the sense amplifiers connected downstream, then read errors result.
The problem is solved, for example, in the publication N.C.C. Lou, IEDM 1988, page 588 et seq., by moving the transistor, which is usually situated next to the trench capacitor, to a position situated above the trench capacitor. As a result, the trench can take up a part of the substrate surface that is conventionally reserved for the transistor. Through such a configuration, the trench capacitor and the transistor share part of the substrate surface. The configuration is made possible by growing an epitaxial layer above the trench capacitor.
What is problematic, however, is the electrical connection of the trench capacitor to the transistor. To that end, N.C.C. Lou, TEDM 1988, page 588 et seq., describes a method in which lithographic alignment of the individual lithographic planes with respect to one another requires a minimum distance between trench capacitor and transistor. As a result, the memory cells in a memory cell array require a relatively large area and are unsuitable for integration in a large-scale integrated cell array.
Furthermore, Japanese Patent Document 10-321813 A, corresponding to U.S. Pat. No. 5,998,821 to Hieda et al., discloses a DRAM memory cell in which the selection transistor is situated in a subsequently grown, epitaxial silicon layer directly above the trench capacitor. A so-called “surface strap” diffusion layer
35
is provided to electrically connect the inner capacitor electrode
25
to the source/drain regions
34
.
Furthermore, U.S. Pat. No. 5,843,820 to Lu discloses a DRAM memory cell in which the selection transistor is situated in a subsequently grown, epitaxial silicon layer above a horizontal trench capacitor.
However, U.S. Pat. No. 5,410,503 to Anzai discloses a memory cell having a selection transistor and a trench capacitor. In such a case, the selection transistor is disposed in a subsequently grown, epitaxial silicon layer and horizontally adjoins the trench capacitor, so that the source electrode is electrically conductively connected to the outer capacitor electrode.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory with trench capacitor and selection transistor and method for fabricating it that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that electrically connects the trench capacitor to the transistor in a way that is suitable for a large scale integrated cell array.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory, including a substrate and at least two memory cells. Each of the memory cells is disposed at least partly in the substrate. Each of the memory cells has a transistor having a drain region, a source region, and a channel, a first word line disposed between the source region and the drain region, a trench capacitor having an inner electrode, an outer electrode, and a dielectric layer disposed between the inner electrode and the outer electrode, a trench disposed in the substrate and filled with a conductive trench filling forming the

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