Memory with sequential mode

Static information storage and retrieval – Addressing – Sequential

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Details

365230, G11C 800

Patent

active

046807381

ABSTRACT:
A memory comprising a plurality of memory cells, a column decoder, a row decoder, a plurality of shift registers and a multiplexer is provided for addressing the memory cells in a conventional manner or in a high-speed sequential mode. In the sequential mode alternate cells from each of two sets of cells are addressed and their contents provided on a data output line, or data presented to them on a data input line, at a system clock rate which is much faster than the conventional mode.

REFERENCES:
patent: 4281401 (1981-07-01), Redwine et al.
patent: 4321695 (1982-03-01), Redwine et al.

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