Memory with sequential data transfer scheme

Details Memory with sequential data transfer scheme Memory with sequential data transfer scheme

1994-03-09

1997-02-04

Swann, Tod R.

395431, G06F 1200

Patent

active

056008198

ABSTRACT:
A memory array area of a semiconductor chip is divided into a plurality of partial memories. Each partial memory is provided with a register. The distance between adjacent registers is set shorter than a maximum distance which that data can travel in the memory in one data transfer cycle defined by a clock signal. These registers are serially connected and provides a path through which addresses, input data, and control signals are transferred to desired partial memories in synchronism with the clock signal. Output data and status signals are also transferred through these registers to a memory output terminal in synchronism with the clock signal.

REFERENCES:
patent: 4958276 (1990-09-01), Kiuchi
patent: 5239215 (1993-08-01), Yamaguchi
patent: 5325503 (1994-06-01), Stevens
patent: 5410670 (1995-04-01), Hansen

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