Memory with selective intervention error checking and correcting

Details Memory with selective intervention error checking and correcting Memory with selective intervention error checking and correcting

1978-12-26

1981-02-03

Atkinson, Charles E.

Excavating

371 13, G06F 1110, G11C 2900

Patent

active

042492530

ABSTRACT:
A memory system wherein data is stored along with a SEC-DED error detecting and correcting code. Means are provided for selecting either a direct readout path for data from the memory when no readout errors have been detected for the memory address being accessed, or an alternate readout path including circuits for checking and correcting errors when an error condition has been detected. An auxiliary memory is provided for storing error flag bits indicating memory zones which have produced erroneous readouts, whereby the system is controlled such that high speed direct read cycles are executed for no-error memory zones and optimum memory accessing time is achieved without sacrificing the reliability achieved through use of the error correcting codes.

REFERENCES:
patent: 3949208 (1976-04-01), Carter
patent: 4077565 (1978-03-01), Nibby, Jr. et al.
patent: 4112502 (1978-09-01), Scheuneman
Wolff, Main Storage Error Correction, IBM Technical Disclosure Bulletin, vol. 10, Mar. 1968, pp. 1561-1562.

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