Memory with selectable single cell or twin cell configuration

Details Memory with selectable single cell or twin cell configuration Memory with selectable single cell or twin cell configuration

2007-08-07

2007-08-07

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010

Reexamination Certificate

active

11025561

ABSTRACT:
A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line activation configurations include three twin cell word line activation configurations and a single cell word line activation configuration. The row address predecoder is configured for selecting one of four word lines if the single cell word line activation configuration is selected.

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A copy of PCT International Search Report for International Application No. PCT/EP2005/014005 mailed on May 30, 2006 (5 pages).

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