Memory with row redundancy

Details Memory with row redundancy Memory with row redundancy

2002-07-19

2004-03-23

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S200000, C365S236000

Reexamination Certificate

active

06711056

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to memory devices and in particular the present invention relates to a memory with row redundancy and its operation.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in a computer. One type of memory used to store data in a computer is random access memory (RAM). RAM is typically used as main memory in a computer environment. Most RAM is volatile. That is, RAM generally requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, all data stored in the RAM is lost.
Another type of memory is a non-volatile memory. A non-volatile memory is a type of memory that retains stored data when power is turned off. A flash memory is a type of non-volatile memory. An important feature of a flash memory is that it can be erased in blocks instead of one byte at a time. Each block of memory in a memory array of the flash memory comprises rows and columns of memory cells. Many modern computers have their basic I/O system (BIOS) stored on flash memory chips.
As with other memory devices, defects can occur during the manufacture of a flash memory array having rows and columns of memory cells. Typical defects can include bad memory cells, open circuits, shorts between a pair of rows and shorts between a row and column. Shorts typically occur because of the large number of rows and columns of memory cells that have to be placed in close proximity to each other on an integrated circuit. Defects can reduce the yield of the flash memory device. A way to resolve this problem, without discarding the memory device, is to incorporate redundant elements in the memory that selectively replace defective elements. For example, redundant rows are a common form of redundant elements used in flash memory to replace a defective primary row. Redundant columns are another common form of redundant elements used in flash memory to replace a defective primary column.
After a memory die has been manufactured, it is tested for defects. Generally with volatile memory, redundancy circuitry is used to selectively route access requests directed to the defected elements to the redundant elements. Redundancy circuitry can comprise electrical fuses that are selectively “blown” (i.e. open circuited) to disconnect the shorted rows. The redundant rows are then activated to replace the shorted rows. The electrical fuses are generally blown by one of two methods. The first is known as the Ohm heating method. This method involves driving a substantial current through a fuse to melt the fuse's conductive material. The other method is known as the laser method. The laser method uses a laser to cut a fuse's conductive material. Anti-fuse circuitry can also be used. Anti-fuses are normally open and short-circuited (closed) when programmed.
Some memory devices, including some flash memory devices, utilize non-volatile registers to store addresses of primary elements that are designated to be replaced. The addresses of the primary elements are stored in the registers by the manufacturer. The registers are generally coupled to a redundant circuit. The redundant circuit compares address requests to addresses stored in the registers. If an address request matches an address stored in a register, the redundant circuit directs or maps the access request to the redundant row instead of the shorted row.
Generally, the use of redundant elements work well, however, problems can occur if the defect involves shorts between two rows or shorts between a row and a column in the primary array. This is because, even though a redundant row or column is read to or written to instead of the shorted row or column, the short is still embedded in the primary memory array and the defect can effect other elements in the primary memory array. One problem generally arises during pre-program and soft program cycles of an erase operation. An erase operation is an algorithm that typically comprises a pre-programmed cycle, an erase cycle and a soft program cycle. The preprogrammed cycle of an erase operation puts each memory cell in a programmed state by applying a program pulse to each row of memory cells. The soft program cycle or heal cycle corrects any over-erased memory cells after the erase cycle has been completed by applying a soft program pulse to the over-erased memory cells.
Disabling the redundancy circuit during the pre-program and soft program cycle when a row or column is addressed that is shorted to another row is one method of dealing with this problem. This allows the pre-program and soft program cycle to be applied to the shorted rows and columns in the primary memory array. By doing this, the effect of the shorts on other elements in the primary memory array is eliminated or at least minimized.
However, a problem arises when dealing with a row-to-row short. When a first row is addressed that is shorted to a second row and a pre-program pulse of a pre-program cycle is applied or a soft program pulse of a soft program cycle is applied, the second row also receives the respective pre-program pulse or soft program pulse. This creates a conflict between a driver of the first shorted row and the driver of the second shorted row that could lead to a collapse of the voltage supply that is driving the rows. If this were to happen, the memory cells in the first and second rows may not get properly programmed. A method of dealing with this problem is by activating the first row and the second row and simultaneously applying the respective pre-program cycle or soft program cycle to the rows. This in turn, creates another problem when the address is incremented after the respective pre-program cycle or soft program cycle has been completed because the next address will be the second shorted row. A way to skip over the second row is needed or another pre-program cycle or soft program cycle will be applied to the first and second shorted rows. This could potentially place too much charge on the memory cells of the rows.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory that has the ability to reduce exposure of programming voltages to rows shorted together.
SUMMARY
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together or at a second level when four rows of the memory array are shorted together. The control circuitry instructs an address counter, during an erase operation, to increment row addresses of the rows of the memory array by two rows when the bit is at the first level or four rows when the bit is at the second level.
In another embodiment, a memory device is provided. The memory device has a memory array arranged in rows and columns. The memory array has a redundant row for selectively replacing an associated defective row in the memory array. A register for the redundant row to store a redundancy address corresponding to an address of the associated defective row in the memory array and for storing a first or second bit level respectively indicative of two rows or four rows of the memory array shorted together is included. Also included is a redundancy circuit for comparing row addresses of the rows of the memory array to the redundancy address. The memory device has control circuitry to control memory operations. The control circuitry applies a program cycle of an erase operation to two rows of the memory array simultaneously and instructs an address counter to increment the row addresses by two rows when the bit is at the first

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