Memory with phase locked serial input port

Details Memory with phase locked serial input port Memory with phase locked serial input port

1991-11-18

1993-11-09

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36518904, 36518912, G11C 804

Patent

active

052609090

ABSTRACT:
A memory circuit is provided with a phase locked serial input port that is adapted to receive unsynchronized raw serial data. The memory eliminates complex serial input timing problems associated with conventional video RAM, and allows direct connection to high speed external storage devices and communication devices. The memory circuit includes a memory array having an input port and an output port, a serial sequential circuit coupled to the memory array for loading data into the memory array, and a phase locked loop circuit for receiving raw serial data. The phase locked loop circuit is coupled to the serial sequential circuit for providing a synchronized data signal and a clock signal to the serial sequential circuit.

REFERENCES:
patent: 4558436 (1985-12-01), Wagensonner et al.
patent: 4750839 (1988-06-01), Wang et al.
patent: 4912679 (1990-03-01), Shinoda et al.
patent: 4987559 (1991-01-01), Miyauchi et al.

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