Memory with page mode

Static information storage and retrieval – Addressing – Byte or page addressing

Patent

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Details

36523003, 36523006, 3652335, G11C 800

Patent

active

052107230

ABSTRACT:
In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.

REFERENCES:
patent: 4546451 (1985-10-01), Bruce
patent: 4586167 (1986-04-01), Fujishima et al.

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