Memory with level shifting word line driver and method thereof

Details Memory with level shifting word line driver and method thereof Memory with level shifting word line driver and method thereof

2006-05-15

2008-10-21

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S228000, C365S230060, C365S189110

Reexamination Certificate

active

07440354

ABSTRACT:
A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

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