Memory with error detection and correction means

Details Memory with error detection and correction means Memory with error detection and correction means

1975-11-20

1977-06-07

Atkinson, Charles E.

Registers

Transfer mechanism

Traveling pawl

G06F 1100, G11C 2900

Patent

active

040285391

ABSTRACT:
The invention relates to a memory device which initially consists of a number of modules which can be exchanged and wherein no non-correctable storage errors are present. If such errors occur at a later stage, the address of the detective module is applied to an inversion device which is connected between an address input line and the actual memory device. This address actuates the inversion device such that the relevant memory unit becomes the last one in the sequence of memory units. By blocking the highest address, a memory device having a substantially unchanged capacity can thus be automatically realized. By replacement of the defective module at a later stage, the original capacity can be restored. If a second module fails after the first module has become defective, the sequence can be modified again etc., with the result that each time an as large as possible number of modules of the memory device can be addressed in a consecutive sequence.

REFERENCES:
patent: 3781826 (1973-12-01), Beausoleil
patent: 3796996 (1974-03-01), Curley et al.
patent: 3803560 (1974-04-01), DeVoy et al.
patent: 3872291 (1975-03-01), Hunter, II
patent: 3917933 (1975-11-01), Scheuneman et al.

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