Memory with combined synchronous burst and bus efficient functio

Details Memory with combined synchronous burst and bus efficient functio Memory with combined synchronous burst and bus efficient functio

1999-09-02

2000-12-19

Nelms, David

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365233, G11C 800

Patent

active

061635006

ABSTRACT:
A memory device is described which is operable in both a synchronous mode and a bus efficient mode (BE). Address and data register circuitry provide multiple propagation paths which can be selected based upon the operating mode and function performed. These features allow one memory device to be manufactured for multiple commercial applications. The address and data register circuitry have first and second paths, wherein the second paths are longer than the first paths. Control circuitry is provided to select the desired paths. During a synchronous and BE read operations, the first path of both the address and data register circuitry is selected. During BE write operations, the second path of the address register circuitry is selected. If the BE is operating in non-pipelined mode, the second path of the data register circuitry is selected. Finally, if the BE is operating in pipelined mode, the first path of the data register circuitry is selected following a write operation, and the second path of the data register circuitry is selected following a read operation.

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"2.25Mb ZBT SRAM Product Specifications", Micron Technology, Inc., (Sep. 1997).
"Syncburst SRAM Product Guide", Micron Technology, Inc., (Feb. 1998).

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