Memory with clocked sense amplifier

Details Memory with clocked sense amplifier Memory with clocked sense amplifier

2006-03-29

2008-09-30

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S154000, C365S149000, C365S205000

Reexamination Certificate

active

07430151

ABSTRACT:
In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory array for successively accessing predetermined bit locations in the memory array during successive memory cycles. The control circuitry senses data within the memory array at a beginning of a predetermined memory cycle. Timing of the memory cycle is determined from a single external clock edge of a memory system clock. During a single memory cycle the memory initially performs the function of sensing followed by at least the functions of precharging the bit lines, addressing and developing a signal to be sensed. In one form each of the successive memory cycles is a period of time of no more than a single period of the memory system clock.

REFERENCES:
patent: 5563834 (1996-10-01), Longway et al.
patent: 6181626 (2001-01-01), Brown
patent: 6201757 (2001-03-01), Ward et al.
patent: 6952040 (2005-10-01), Chau et al.
patent: 2007/0064462 (2007-03-01), Matsui

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