Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-06-11
2010-02-16
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050
Reexamination Certificate
active
07663965
ABSTRACT:
An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.
REFERENCES:
patent: 6512719 (2003-01-01), Fujisawa et al.
patent: 7362619 (2008-04-01), Morzano et al.
patent: 7370140 (2008-05-01), Sartore et al.
patent: 7376021 (2008-05-01), Heo et al.
patent: 2003/0223300 (2003-12-01), Schroder et al.
Roewer Falk
Schnabel Florian
Sichert Christian
Edell Shapiro & Finnan LLC
Hidalgo Fernando N
Ho Hoai V
Qimonda AG
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