Memory wait cycle control system for microcomputer

Details Memory wait cycle control system for microcomputer Memory wait cycle control system for microcomputer

1993-05-12

1997-04-08

Lane, Jack A.

39549702, 395481, G06F 1200

Patent

active

056196695

ABSTRACT:
A memory control system comprises a plurality of base address registers each for designating a base address of a corresponding memory block, and a corresponding number of block size registers each for designating the size of the corresponding memory block. An output of one base address register and an output of be corresponding block size register are supplied to a corresponding comparator, and compared with MSB bits of a memory access address. An output of the comparator selectively activates, in accordance with the order of priority, a corresponding memory control register which designates a wait state number for the corresponding memory block, so that the wait state number is outputted.

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